| Message ID | 20231019022300.1588041-1-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mp: Add NPU Node | expand |
Hi Adam, thanks for the patch I tried a similar one. Am Donnerstag, 19. Oktober 2023, 04:23:00 CEST schrieb Adam Ford: > The NPU is based on the Vivante GC8000 and it enumerates as > > etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002 > > Signed-off-by: Adam Ford <aford173@gmail.com> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index > c9a610ba4836..1ef8d17726ac 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > @@ -2012,6 +2012,25 @@ vpumix_blk_ctrl: blk-ctrl@38330000 { > interconnect-names = "g1", "g2", "vc8000e"; > }; > > + npu: npu@38500000 { > + compatible = "vivante,gc"; > + reg = <0x38500000 0x20000>; Do you have some more information about the actual memory range? RM says 2MiB, but NPU memory map lists up to 0x664. > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MP_CLK_NPU_ROOT>, > + <&clk IMX8MP_CLK_NPU_ROOT>, > + <&clk IMX8MP_CLK_ML_AXI>, > + <&clk IMX8MP_CLK_ML_AHB>; > + clock-names = "core", "shader", "bus", "reg"; > + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, > + <&clk IMX8MP_CLK_ML_AXI>, > + <&clk IMX8MP_CLK_ML_AHB>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, > + <&clk IMX8MP_SYS_PLL1_800M>, > + <&clk IMX8MP_SYS_PLL1_800M>; > + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; 1GHz for ML_CLK_ROOT is only available in overdrive mode, 800MHz in nominal mode. See datasheet IMX8MPIEC Rev 2.1. I don't think it's a good idea to configure for overdrive mode by default. Same goes for CLK_ML_AHB regarding 400 vs. 300 MHz. Best regards, Alexander > + power-domains = <&pgc_mlmix>; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>,
On Thu, Oct 19, 2023 at 1:00 AM Alexander Stein <alexander.stein@ew.tq-group.com> wrote: > > Hi Adam, > > thanks for the patch I tried a similar one. > > Am Donnerstag, 19. Oktober 2023, 04:23:00 CEST schrieb Adam Ford: > > The NPU is based on the Vivante GC8000 and it enumerates as > > > > etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002 > > > > Signed-off-by: Adam Ford <aford173@gmail.com> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index > > c9a610ba4836..1ef8d17726ac 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > @@ -2012,6 +2012,25 @@ vpumix_blk_ctrl: blk-ctrl@38330000 { > > interconnect-names = "g1", "g2", "vc8000e"; > > }; > > > > + npu: npu@38500000 { > > + compatible = "vivante,gc"; > > + reg = <0x38500000 0x20000>; > > Do you have some more information about the actual memory range? RM says 2MiB, > but NPU memory map lists up to 0x664. I do not. The RM lists 3850_0000 - 386F_FFFF, so I should have put an extra 0 in there. Sorry about that. I will fix in the next rev. > > > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MP_CLK_NPU_ROOT>, > > + <&clk IMX8MP_CLK_NPU_ROOT>, > > + <&clk IMX8MP_CLK_ML_AXI>, > > + <&clk IMX8MP_CLK_ML_AHB>; > > + clock-names = "core", "shader", "bus", "reg"; > > + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, > > + <&clk IMX8MP_CLK_ML_AXI>, > > + <&clk IMX8MP_CLK_ML_AHB>; > > + assigned-clock-parents = <&clk > IMX8MP_SYS_PLL2_1000M>, > > + <&clk > IMX8MP_SYS_PLL1_800M>, > > + <&clk > IMX8MP_SYS_PLL1_800M>; > > + assigned-clock-rates = <1000000000>, > <800000000>, <400000000>; > > 1GHz for ML_CLK_ROOT is only available in overdrive mode, 800MHz in nominal > mode. See datasheet IMX8MPIEC Rev 2.1. I don't think it's a good idea to > configure for overdrive mode by default. You are right. I looked at the clocking from the downstream tree to see what their clocks were, and it didn't occur to me to double check against the datasheet. > Same goes for CLK_ML_AHB regarding 400 vs. 300 MHz. I'll update both and submit a V2. adam > > Best regards, > Alexander > > > + power-domains = <&pgc_mlmix>; > > + }; > > + > > gic: interrupt-controller@38800000 { > > compatible = "arm,gic-v3"; > > reg = <0x38800000 0x10000>, > > > -- > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany > Amtsgericht München, HRB 105018 > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider > http://www.tq-group.com/ > >
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c9a610ba4836..1ef8d17726ac 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -2012,6 +2012,25 @@ vpumix_blk_ctrl: blk-ctrl@38330000 { interconnect-names = "g1", "g2", "vc8000e"; }; + npu: npu@38500000 { + compatible = "vivante,gc"; + reg = <0x38500000 0x20000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + clock-names = "core", "shader", "bus", "reg"; + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <1000000000>, <800000000>, <400000000>; + power-domains = <&pgc_mlmix>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>,
The NPU is based on the Vivante GC8000 and it enumerates as etnaviv-gpu 38500000.npu: model: GC8000, revision: 8002 Signed-off-by: Adam Ford <aford173@gmail.com>