From patchwork Thu Oct 19 08:23:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei-Ning Huang X-Patchwork-Id: 13428449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59177CDB465 for ; Thu, 19 Oct 2023 08:24:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: Mime-Version:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=f4McfF8lpRM/NgPBGRSXMLxcn/t0Jc/OaToPNRxzjkw=; b=iGX J3AzReVl0J2kXR0PUhDuW84gsqqC5cShNEpx55sI+ge3U+lxMEyGHFFRcSbubAEk35hExDt8TbJT1 2OGW30pirf8WYPWtxw0vKgE6yYI3XA19NrlsJnbYNrHNFrEQgIJc3zTwpVGnvevCdgkbAInFeofaP 2Q9yWBEpUpQgaIVyYQokbX3FNa+sue32vDO03e2Tvd1By2hLlIkOYnq7UZB1110gdtQNG2dcFSr6a TKcfh1wAC7C5+RN8CZ4WJJIT7EKST1HYw/YTxoV+UGrbW5x5rlVvtrDHQMGRFQCK0pTJSqRef0AnV kcapQLJm6SM54AibqvQtTVVuJEyIuaw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qtOKD-00GhoL-0b; Thu, 19 Oct 2023 08:24:13 +0000 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qtOKA-00Ghmd-1N for linux-arm-kernel@lists.infradead.org; Thu, 19 Oct 2023 08:24:11 +0000 Received: by mail-yb1-xb4a.google.com with SMTP id 3f1490d57ef6-d9a45e7e0f9so10670276276.0 for ; Thu, 19 Oct 2023 01:24:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1697703845; x=1698308645; darn=lists.infradead.org; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=Lu+FeCyL3oCgR0FP+gkAe4hCPFiLBzzy7yX8rQh0MDk=; b=12/CVNxdpHBjcEhCsmowJTn8+7Hm1CN9QMXxAQzMx2xA3VBWFDHBeRRzv9hGRXS/IR somUCLrTG1R9H9KL85owk1tzxVkCBVOBIM9fyTSsLDcqnls/3qAD3FK3doKjsMEuJvbL C0Y0UinEiyhgao0vYYfsuanJs2jPoTyq2Dtrc19vEJ/Y8yuqzwQnU/38sxtgp6AyPo4v ACO/GaPR+UJshO/Cw9I2VUY3IqHrBSAT0R+fjhfGDDgkxf7F97f4M/rCVtrq4IQ87xog SZ30IU9RqHjM6ef+iU2RjT9KImhoyY0Y3bktlDp/QoJGXzCVIcV0IHwt4vNaG1wvOfGS sEfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697703845; x=1698308645; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=Lu+FeCyL3oCgR0FP+gkAe4hCPFiLBzzy7yX8rQh0MDk=; b=lMqE45Y43GmREixrK27pJZVg8qpRwQZnVBdG6rnDEPCRVWxnQvAjDSo8y6U3TX+NVe UBDRRjS5MmGGLWqq+B/qMB3ibF80/2iUHpHE7YTmofhtQtwpz8X/MgzHnsXwcqsOTPZe 8aFZWHlxe1UXg+vnGDzXaWfLpLCG5LAqt+QrEsM26kAzwTPSeq/Cj0cGBEc1WUXmUhg/ ELCeKCAa2qznaebQZrm5Y5PEQDce0SZKBi1QmbSUCphuxbnbSNjXhI+Q5oDFPdk+Cfo7 cRYZdwO5WlB/szOPQ6XrJTBX9RiST9rq6SifWsuNmKM/9vg6f2KhNgZnmssljocRSviJ uOGA== X-Gm-Message-State: AOJu0YxrseQr0oRYhBx+5/byVBQJi3F/gm0MHzvdeQZtzWJbDKXWzflw swvR4w677EaUhaM6PQAj5qoaupOWHgrxlemPPWcng58KtohSFNW/N8oJ/D4wE7qRsgEZjX3VL+1 rcXyjc/C9m59nJ/1zp7if2uLcgdV340/6nlp/ftyGsofsi77iBTTMkOsJzwt547D3K/D7unT5gl F/awhXFzg= X-Google-Smtp-Source: AGHT+IEirk34VW4JdGjVi2e1kKViuhhou/6R9Dp0JdkMnk46P/V54IcYs4vDzb7/EWCv6K5nHuC1EamwU9FI X-Received: from wnhuang-p920.tpe.corp.google.com ([2401:fa00:fc:200:8537:873c:b8ab:6b48]) (user=wnhuang job=sendgmr) by 2002:a05:6902:134a:b0:d9a:58e0:c7c7 with SMTP id g10-20020a056902134a00b00d9a58e0c7c7mr34535ybu.1.1697703845044; Thu, 19 Oct 2023 01:24:05 -0700 (PDT) Date: Thu, 19 Oct 2023 16:23:57 +0800 Mime-Version: 1.0 X-Mailer: git-send-email 2.42.0.655.g421f12c284-goog Message-ID: <20231019082357.1505047-1-wnhuang@google.com> Subject: [PATCH] coresight: etm4x: Allow configuring cycle count threshold From: Wei-Ning Huang To: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org, suzuki.poulose@arm.com, james.clark@arm.com, leo.yan@linaro.org Cc: linux-kernel@vger.kernel.org, Wei-Ning Huang X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231019_012410_463745_192F6761 X-CRM114-Status: GOOD ( 11.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allow userspace to configure cycle count threshold through perf_event_attr config. The last high 12-bit of config value is used to store the cycle count threshold. Signed-off-by: Wei-Ning Huang --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++++- include/linux/coresight-pmu.h | 14 ++++++++------ tools/include/linux/coresight-pmu.h | 14 ++++++++------ 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 77b0271ce6eb..155441668b4a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -645,6 +645,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, struct perf_event_attr *attr = &event->attr; unsigned long cfg_hash; int preset; + u64 cyc_threadhold; /* Clear configuration from previous run */ memset(config, 0, sizeof(struct etmv4_config)); @@ -667,7 +668,10 @@ static int etm4_parse_event_config(struct coresight_device *csdev, if (attr->config & BIT(ETM_OPT_CYCACC)) { config->cfg |= TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ - config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + cyc_threshold = ((attr->config >> ETM_OPT_CYC_THRESHOLD_SHIFT) & + ETM_OPT_CYC_THRESHOLD_MASK; + config->ccctlr = cyc_threshold ? cyc_threshold : + ETM_CYC_THRESHOLD_DEFAULT; } if (attr->config & BIT(ETM_OPT_TS)) { /* diff --git a/include/linux/coresight-pmu.h b/include/linux/coresight-pmu.h index 51ac441a37c3..14f48658ff1c 100644 --- a/include/linux/coresight-pmu.h +++ b/include/linux/coresight-pmu.h @@ -29,12 +29,14 @@ * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and * directly use below macros as config bits. */ -#define ETM_OPT_BRANCH_BROADCAST 8 -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_CTXTID2 15 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 +#define ETM_OPT_BRANCH_BROADCAST 8 +#define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 +#define ETM_OPT_CTXTID2 15 +#define ETM_OPT_TS 28 +#define ETM_OPT_RETSTK 29 +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52 +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_BB 3 diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index 51ac441a37c3..14f48658ff1c 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -29,12 +29,14 @@ * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and * directly use below macros as config bits. */ -#define ETM_OPT_BRANCH_BROADCAST 8 -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_CTXTID2 15 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 +#define ETM_OPT_BRANCH_BROADCAST 8 +#define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 +#define ETM_OPT_CTXTID2 15 +#define ETM_OPT_TS 28 +#define ETM_OPT_RETSTK 29 +#define ETM_OPT_CYC_THRESHOLD_SHIFT 52 +#define ETM_OPT_CYC_THRESHOLD_MASK 0xfff /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_BB 3