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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id o7-20020a05651205c700b005056ccb222asm2148654lfo.105.2023.10.24.08.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 08:12:32 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 86FF91645; Tue, 24 Oct 2023 17:12:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160351; bh=nOWykBjoXapYzbbqt/B6vaxHD5OyGUKgl7kHm6hJUts=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CfqMVtKXdWU4nwYfFVHbHd9bg4JIR981xpUEQ0AEOJcJjjGKbaKWn4SYdsFRNw4W5 ovfAgmi81UefW/sTD7NR9/3uhC0KEK26qJpEvWUyouNUZf4AtXdEbYwUgJW1wECZRB 1fHoIMOyt5dcRRtT2jqNjuC3HxaHMZVqtgkYxG3o= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 57FF514E7; Tue, 24 Oct 2023 17:10:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160246; bh=nOWykBjoXapYzbbqt/B6vaxHD5OyGUKgl7kHm6hJUts=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WAnZ5gtPK8mM3eEH4aTkJGHHxRvBNJtNK4kGrk0CYhTG4AEKnQKNIPRPCcuti4T1E 7oJX1wj0eJ132vMInhvaOTYDmRkFXrouTOzfMVtn3QlFbek8AjJWbl+NL8vVFrDoIt IHHPQpg9jT9kIiC17HA5YFoWQQzPPZ0VnyYB0UAk= From: Niklas Cassel To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Shawn Lin , Simon Xue Cc: Damien Le Moal , Sebastian Reichel , Niklas Cassel , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 3/4] dt-bindings: PCI: dwc: rockchip: Add dma properties Date: Tue, 24 Oct 2023 17:10:10 +0200 Message-ID: <20231024151014.240695-4-nks@flawful.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231024151014.240695-1-nks@flawful.org> References: <20231024151014.240695-1-nks@flawful.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231024_081234_736442_04D3DEEE X-CRM114-Status: GOOD ( 11.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Niklas Cassel Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml using: allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# and snps,dw-pcie.yaml does have the dma properties defined, in order to be able to use these properties, while still making sure 'make CHECK_DTBS=y' pass, we need to add these properties to rockchip-dw-pcie.yaml. Signed-off-by: Niklas Cassel --- .../bindings/pci/rockchip-dw-pcie.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 229f8608c535..633f8e0e884f 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -35,6 +35,7 @@ properties: - description: Rockchip designed configuration registers - description: Config registers - description: iATU registers + - description: eDMA registers reg-names: minItems: 3 @@ -43,6 +44,7 @@ properties: - const: apb - const: config - const: atu + - const: dma clocks: minItems: 5 @@ -65,6 +67,7 @@ properties: - const: pipe interrupts: + minItems: 5 items: - description: Combined system interrupt, which is used to signal the following @@ -88,14 +91,31 @@ properties: interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. + - description: + Indicates that the eDMA Tx/Rx transfer is complete or that an + error has occurred on the corresponding channel. interrupt-names: + minItems: 5 items: - const: sys - const: pmc - const: msg - const: legacy - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 legacy-interrupt-controller: description: Interrupt controller node for handling legacy PCI interrupts.