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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id k16-20020ac24f10000000b00507c5216aeasm2170277lfr.263.2023.10.24.08.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Oct 2023 08:12:52 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id BAA1F1646; Tue, 24 Oct 2023 17:12:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160371; bh=ErqCJiP8U44ISh4Im9EcpFWgOzEosEpfBHoDJ+9Kgdw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a6XTnA0RrJtadaLvr5GHrTZu9Fm+nIAvpOL2VT9a4z4fPnNArrlfrMRw12unO3Hzr RYDsnEXTcCy5C88zZBy/gCoaC/5uc99EcPOGovnMDjAnj3pBnshJQb6ZerWVqRiLdb ewHQJ6PasJO2zPzj0Z+GLrCsdktzJdTdcJcqdtjI= Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id 14D5015E1; Tue, 24 Oct 2023 17:10:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1698160247; bh=ErqCJiP8U44ISh4Im9EcpFWgOzEosEpfBHoDJ+9Kgdw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YPetIezbIGPz/6ySQtofIO1XKUtjvcIGK/RwOaRqbMiPAspV+G+wA19XlHTfwKvMH k/lMSgd2DckEIDOIiVS1bMBWcP7XbW5zAbz7sqw9MpjZnpQqKtAbhr90knfA8lZo0u s9tgKPeOxCbawAWwZVFr7XzoLGyJVZHmuyY/0MeQ= From: Niklas Cassel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Damien Le Moal , Sebastian Reichel , Niklas Cassel , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 4/4] arm64: dts: rockchip: add missing rk3588 PCIe dma properties Date: Tue, 24 Oct 2023 17:10:11 +0200 Message-ID: <20231024151014.240695-5-nks@flawful.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231024151014.240695-1-nks@flawful.org> References: <20231024151014.240695-1-nks@flawful.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231024_081254_834448_D8D5FCE4 X-CRM114-Status: GOOD ( 13.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Niklas Cassel The rk3588 has 5 PCIe controllers, however, according the the rk3588 TRM (Technical Reference Manual), only pcie3x4 supports the embedded DMA controller (eDMA) on the DWC PCIe controller. The size of the eDMA region equals to: 0x200 + MAX(NUM_DMA_RD_CHAN, NUM_DMA_WR_CHAN) * 0x200. Where for each 0x200 region, the registers controlling the write channel starts at offset 0x0, and the registers controlling the read channel starts at offset 0x100. pcie3x4 has two DMA read channels and two DMA write channels, so it has size: 0x200 + max(2, 2) * 0x200 = 0x600 On the rk3588 based rock-5b board, when building with CONFIG_DW_EDMA=y: Before this patch, only the iATUs are detected: rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G After this patch, both the iATUs and the eDMA channels are detected: rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G rockchip-dw-pcie a40000000.pcie: eDMA: unroll T, 2 wr, 2 rd Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index d7998a9c0c43..e072f5fe655d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -101,8 +101,13 @@ pcie3x4: pcie@fe150000 { , , , - ; - interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, @@ -122,8 +127,9 @@ pcie3x4: pcie@fe150000 { reg = <0xa 0x40000000 0x0 0x00300000>, <0x0 0xfe150000 0x0 0x00010000>, <0x0 0xf0000000 0x0 0x00100000>, - <0xa 0x40300000 0x0 0x00002000>; - reg-names = "dbi", "apb", "config", "atu"; + <0xa 0x40300000 0x0 0x00002000>, + <0xa 0x40380000 0x0 0x00000600>; + reg-names = "dbi", "apb", "config", "atu", "dma"; resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; reset-names = "pwr", "pipe"; status = "disabled";