@@ -9,6 +9,9 @@
#include <asm/cp15.h>
#include <asm/cputype.h>
+/* Mask for writable bits */
+#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff
+
#define PMCCNTR __ACCESS_CP15_64(0, c9)
#define PMCR __ACCESS_CP15(c9, 0, c12, 0)
@@ -11,6 +11,10 @@
#include <asm/cpufeature.h>
#include <asm/sysreg.h>
+/* Mask for writable bits */
+#define ARMV8_PMU_EVTYPE_MASK (0xc800ffffUL | ARMV8_PMU_EVTYPE_TH | \
+ ARMV8_PMU_EVTYPE_TC)
+
#define RETURN_READ_PMEVCNTRN(n) \
return read_sysreg(pmevcntr##n##_el0)
static inline unsigned long read_pmevcntrn(int n)
@@ -228,7 +228,8 @@
/*
* PMXEVTYPER: Event selection reg
*/
-#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */
+#define ARMV8_PMU_EVTYPE_TH GENMASK(43, 32)
+#define ARMV8_PMU_EVTYPE_TC GENMASK(63, 61)
#define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */
/*
FEAT_PMUv3_TH (Armv8.8) adds two new fields to PMEVTYPER, so include them in the mask. These aren't writable on 32 bit kernels as they are in the high part of the register, so split the mask definition to the asm files for each platform. Despite not being used on aarch32, TH and TC macros are added to the shared header file, because will be used in arm_pmuv3.c which is compiled for both platforms. Signed-off-by: James Clark <james.clark@arm.com> --- arch/arm/include/asm/arm_pmuv3.h | 3 +++ arch/arm64/include/asm/arm_pmuv3.h | 4 ++++ include/linux/perf/arm_pmuv3.h | 3 ++- 3 files changed, 9 insertions(+), 1 deletion(-)