From patchwork Wed Oct 25 09:57:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: James Clark X-Patchwork-Id: 13435890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 495AAC0032E for ; Wed, 25 Oct 2023 09:58:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2hUnbfCjH4YEuMJnZFjyt2qoTs7o4wCETFrdu9N2G/4=; b=Pis3e8wUhmSpcl 954KiFI5CgD7OogwxW2zuNFnX09y9zYtmfLvA2ZMJPyRYMhg025aOo04DrgsGLE14M0AjMN7zcZ3o ZxImq8hILsx6cb6FxjQRxqfvYpqBzg0IejNLsCDvkIVCTDyNNevRTd98YwfFIiRDXICa9ya7Cb5SO t7qZ5R5xtPnAP/TdpN6ecYW6fAJHokqw30ujcOmpuviOYBhgIHnBm/lS6SMWTkW8T82YzeGCUDdND jsRYumwNlwb0rRMd6oYTrC3lAXNKCB6XjnO3RdEfhljyc6Km6QavbtRFNhjZ4h1vTOqxa6okasHtk /7G9/f0cMjb3UhO9qSPg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvadz-00Bt99-2o; Wed, 25 Oct 2023 09:57:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvadu-00Bt7Y-1C for linux-arm-kernel@lists.infradead.org; Wed, 25 Oct 2023 09:57:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 937582F4; Wed, 25 Oct 2023 02:58:17 -0700 (PDT) Received: from e127643.arm.com (unknown [10.57.70.16]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AB5953F738; Wed, 25 Oct 2023 02:57:33 -0700 (PDT) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, suzuki.poulose@arm.com, oliver.upton@linux.dev Cc: kvmarm@lists.linux.dev, James Clark , Catalin Marinas , Will Deacon , Jonathan Corbet , Russell King , Mark Rutland , Marc Zyngier , Zaid Al-Bassam , Reiji Watanabe , Geert Uytterhoeven , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/3] arm: perf: Include threshold control fields valid in PMEVTYPER mask Date: Wed, 25 Oct 2023 10:57:03 +0100 Message-Id: <20231025095710.1559601-2-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025095710.1559601-1-james.clark@arm.com> References: <20231025095710.1559601-1-james.clark@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231025_025738_460869_0ED76B77 X-CRM114-Status: GOOD ( 14.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org FEAT_PMUv3_TH (Armv8.8) adds two new fields to PMEVTYPER, so include them in the mask. These aren't writable on 32 bit kernels as they are in the high part of the register, so split the mask definition to the asm files for each platform. Despite not being used on aarch32, TH and TC macros are added to the shared header file, because will be used in arm_pmuv3.c which is compiled for both platforms. Signed-off-by: James Clark --- arch/arm/include/asm/arm_pmuv3.h | 3 +++ arch/arm64/include/asm/arm_pmuv3.h | 4 ++++ include/linux/perf/arm_pmuv3.h | 3 ++- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h index 72529f5e2bed..491310133d09 100644 --- a/arch/arm/include/asm/arm_pmuv3.h +++ b/arch/arm/include/asm/arm_pmuv3.h @@ -9,6 +9,9 @@ #include #include +/* Mask for writable bits */ +#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff + #define PMCCNTR __ACCESS_CP15_64(0, c9) #define PMCR __ACCESS_CP15(c9, 0, c12, 0) diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h index 18dc2fb3d7b7..4faf4f7385a5 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -11,6 +11,10 @@ #include #include +/* Mask for writable bits */ +#define ARMV8_PMU_EVTYPE_MASK (0xc800ffffUL | ARMV8_PMU_EVTYPE_TH | \ + ARMV8_PMU_EVTYPE_TC) + #define RETURN_READ_PMEVCNTRN(n) \ return read_sysreg(pmevcntr##n##_el0) static inline unsigned long read_pmevcntrn(int n) diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h index 9c226adf938a..ddd1fec86739 100644 --- a/include/linux/perf/arm_pmuv3.h +++ b/include/linux/perf/arm_pmuv3.h @@ -228,7 +228,8 @@ /* * PMXEVTYPER: Event selection reg */ -#define ARMV8_PMU_EVTYPE_MASK 0xc800ffff /* Mask for writable bits */ +#define ARMV8_PMU_EVTYPE_TH GENMASK(43, 32) +#define ARMV8_PMU_EVTYPE_TC GENMASK(63, 61) #define ARMV8_PMU_EVTYPE_EVENT 0xffff /* Mask for EVENT bits */ /*