Message ID | 20231031022729.2347871-1-0x1207@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [net,v3] net: stmmac: xgmac: Enable support for multiple Flexible PPS outputs | expand |
On 10/30/2023 7:27 PM, Furong Xu wrote: > From XGMAC Core 3.20 and later, each Flexible PPS has individual PPSEN bit > to select Fixed mode or Flexible mode. The PPSEN must be set, or it stays > in Fixed PPS mode by default. > XGMAC Core prior 3.20, only PPSEN0(bit 4) is writable. PPSEN{1,2,3} are > read-only reserved, and they are already in Flexible mode by default, our > new code always set PPSEN{1,2,3} do not make things worse ;-) > > Fixes: 95eaf3cd0a90 ("net: stmmac: dwxgmac: Add Flexible PPS support") > Reviewed-by: Serge Semin <fancer.lancer@gmail.com> > Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> > Signed-off-by: Furong Xu <0x1207@gmail.com> > --- > Changes in v3: > - Tagged Fixes: and sent through net instead of net-next, thanks Jacob Keller. > Thanks! -Jake
Hello: This patch was applied to netdev/net.git (main) by David S. Miller <davem@davemloft.net>: On Tue, 31 Oct 2023 10:27:29 +0800 you wrote: > From XGMAC Core 3.20 and later, each Flexible PPS has individual PPSEN bit > to select Fixed mode or Flexible mode. The PPSEN must be set, or it stays > in Fixed PPS mode by default. > XGMAC Core prior 3.20, only PPSEN0(bit 4) is writable. PPSEN{1,2,3} are > read-only reserved, and they are already in Flexible mode by default, our > new code always set PPSEN{1,2,3} do not make things worse ;-) > > [...] Here is the summary with links: - [net,v3] net: stmmac: xgmac: Enable support for multiple Flexible PPS outputs https://git.kernel.org/netdev/net/c/db456d90a4c1 You are awesome, thank you!
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 7a8f47e7b728..a4e8b498dea9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -259,7 +259,7 @@ ((val) << XGMAC_PPS_MINIDX(x)) #define XGMAC_PPSCMD_START 0x2 #define XGMAC_PPSCMD_STOP 0x5 -#define XGMAC_PPSEN0 BIT(4) +#define XGMAC_PPSENx(x) BIT(4 + (x) * 8) #define XGMAC_PPSx_TARGET_TIME_SEC(x) (0x00000d80 + (x) * 0x10) #define XGMAC_PPSx_TARGET_TIME_NSEC(x) (0x00000d84 + (x) * 0x10) #define XGMAC_TRGTBUSY0 BIT(31) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c index f352be269deb..453e88b75be0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -1178,7 +1178,19 @@ static int dwxgmac2_flex_pps_config(void __iomem *ioaddr, int index, val |= XGMAC_PPSCMDx(index, XGMAC_PPSCMD_START); val |= XGMAC_TRGTMODSELx(index, XGMAC_PPSCMD_START); - val |= XGMAC_PPSEN0; + + /* XGMAC Core has 4 PPS outputs at most. + * + * Prior XGMAC Core 3.20, Fixed mode or Flexible mode are selectable for + * PPS0 only via PPSEN0. PPS{1,2,3} are in Flexible mode by default, + * and can not be switched to Fixed mode, since PPSEN{1,2,3} are + * read-only reserved to 0. + * But we always set PPSEN{1,2,3} do not make things worse ;-) + * + * From XGMAC Core 3.20 and later, PPSEN{0,1,2,3} are writable and must + * be set, or the PPS outputs stay in Fixed PPS mode by default. + */ + val |= XGMAC_PPSENx(index); writel(cfg->start.tv_sec, ioaddr + XGMAC_PPSx_TARGET_TIME_SEC(index));