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Fri, 3 Nov 2023 21:53:36 GMT Received: from hyd-lablnx450.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Fri, 3 Nov 2023 14:53:31 -0700 From: Bibek Kumar Patro To: , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH 2/3] iommu/arm-smmu: add ACTLR data and support for SM8550 Date: Sat, 4 Nov 2023 03:21:23 +0530 Message-ID: <20231103215124.1095-3-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231103215124.1095-1-quic_bibekkum@quicinc.com> References: <20231103215124.1095-1-quic_bibekkum@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: M2pdkuPqEFYEHa-TVOAKW_7vv2q7NHzx X-Proofpoint-ORIG-GUID: M2pdkuPqEFYEHa-TVOAKW_7vv2q7NHzx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-03_20,2023-11-02_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 mlxlogscore=999 spamscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2311030185 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231103_145345_453923_1CA6E144 X-CRM114-Status: GOOD ( 19.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add ACTLR data table for SM8550 along with support for same including SM8550 specific implementation operations. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 85 +++++++++++++++++++++- 1 file changed, 81 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 68c1f4908473..590b7c285299 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -25,6 +25,64 @@ struct actlr_data { u32 actlr; }; +static const struct actlr_data sm8550_apps_actlr_data[] = { + { 0x18a0, 0x0000, 0x00000103 }, + { 0x18e0, 0x0000, 0x00000103 }, + { 0x0800, 0x0020, 0x00000001 }, + { 0x1800, 0x00c0, 0x00000001 }, + { 0x1820, 0x0000, 0x00000001 }, + { 0x1860, 0x0000, 0x00000001 }, + { 0x0c01, 0x0020, 0x00000303 }, + { 0x0c02, 0x0020, 0x00000303 }, + { 0x0c03, 0x0020, 0x00000303 }, + { 0x0c04, 0x0020, 0x00000303 }, + { 0x0c05, 0x0020, 0x00000303 }, + { 0x0c06, 0x0020, 0x00000303 }, + { 0x0c07, 0x0020, 0x00000303 }, + { 0x0c08, 0x0020, 0x00000303 }, + { 0x0c09, 0x0020, 0x00000303 }, + { 0x0c0c, 0x0020, 0x00000303 }, + { 0x0c0d, 0x0020, 0x00000303 }, + { 0x0c0e, 0x0020, 0x00000303 }, + { 0x0c0f, 0x0020, 0x00000303 }, + { 0x1961, 0x0000, 0x00000303 }, + { 0x1962, 0x0000, 0x00000303 }, + { 0x1963, 0x0000, 0x00000303 }, + { 0x1964, 0x0000, 0x00000303 }, + { 0x1965, 0x0000, 0x00000303 }, + { 0x1966, 0x0000, 0x00000303 }, + { 0x1967, 0x0000, 0x00000303 }, + { 0x1968, 0x0000, 0x00000303 }, + { 0x1969, 0x0000, 0x00000303 }, + { 0x196c, 0x0000, 0x00000303 }, + { 0x196d, 0x0000, 0x00000303 }, + { 0x196e, 0x0000, 0x00000303 }, + { 0x196f, 0x0000, 0x00000303 }, + { 0x19c1, 0x0010, 0x00000303 }, + { 0x19c2, 0x0010, 0x00000303 }, + { 0x19c3, 0x0010, 0x00000303 }, + { 0x19c4, 0x0010, 0x00000303 }, + { 0x19c5, 0x0010, 0x00000303 }, + { 0x19c6, 0x0010, 0x00000303 }, + { 0x19c7, 0x0010, 0x00000303 }, + { 0x19c8, 0x0010, 0x00000303 }, + { 0x19c9, 0x0010, 0x00000303 }, + { 0x19cc, 0x0010, 0x00000303 }, + { 0x19cd, 0x0010, 0x00000303 }, + { 0x19ce, 0x0010, 0x00000303 }, + { 0x19cf, 0x0010, 0x00000303 }, + { 0x1c00, 0x0002, 0x00000103 }, + { 0x1c01, 0x0000, 0x00000001 }, + { 0x1920, 0x0000, 0x00000103 }, + { 0x1923, 0x0000, 0x00000103 }, + { 0x1924, 0x0000, 0x00000103 }, + { 0x1940, 0x0000, 0x00000103 }, + { 0x1941, 0x0004, 0x00000103 }, + { 0x1943, 0x0000, 0x00000103 }, + { 0x1944, 0x0000, 0x00000103 }, + { 0x1947, 0x0000, 0x00000103 }, +}; + static struct qcom_smmu *to_qcom_smmu(struct arm_smmu_device *smmu) { return container_of(smmu, struct qcom_smmu, smmu); @@ -444,6 +502,16 @@ static const struct arm_smmu_impl sdm845_smmu_500_impl = { .tlb_sync = qcom_smmu_tlb_sync, }; + +static const struct arm_smmu_impl sm8550_smmu_500_impl = { + .init_context = qcom_smmu_init_context, + .cfg_probe = qcom_smmu_cfg_probe, + .def_domain_type = qcom_smmu_def_domain_type, + .reset = arm_mmu500_reset, + .write_s2cr = qcom_smmu_write_s2cr, + .tlb_sync = qcom_smmu_tlb_sync, +}; + static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { .init_context = qcom_adreno_smmu_init_context, .def_domain_type = qcom_smmu_def_domain_type, @@ -507,6 +575,11 @@ static const struct qcom_smmu_config qcom_smmu_impl0_cfg = { .reg_offset = qcom_smmu_impl0_reg_offset, }; +static const struct actlr_config sm8550_actlrcfg = { + .adata = sm8550_apps_actlr_data, + .size = ARRAY_SIZE(sm8550_apps_actlr_data), +}; + /* * It is not yet possible to use MDP SMMU with the bypass quirk on the msm8996, * there are not enough context banks. @@ -530,16 +603,20 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = { /* Also no debug configuration. */ }; + +static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = { + .impl = &sm8550_smmu_500_impl, + .adreno_impl = &qcom_adreno_smmu_500_impl, + .cfg = &qcom_smmu_impl0_cfg, + .actlrcfg = &sm8550_actlrcfg, +}; + static const struct qcom_smmu_match_data qcom_smmu_500_impl0_data = { .impl = &qcom_smmu_500_impl, .adreno_impl = &qcom_adreno_smmu_500_impl, .cfg = &qcom_smmu_impl0_cfg, }; -/* - * Do not add any more qcom,SOC-smmu-500 entries to this list, unless they need - * special handling and can not be covered by the qcom,smmu-500 entry. - */ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,msm8996-smmu-v2", .data = &msm8996_smmu_data }, { .compatible = "qcom,msm8998-smmu-v2", .data = &qcom_smmu_v2_data },