diff mbox series

[2/3] perf: arm_spe: Factor out PMSCR set/clear operations

Message ID 20231122084602.53914-3-yangyicong@huawei.com (mailing list archive)
State New, archived
Headers show
Series Enable the profiling of EL0&1 translation regime of ARM SPE | expand

Commit Message

Yicong Yang Nov. 22, 2023, 8:46 a.m. UTC
From: Yicong Yang <yangyicong@hisilicon.com>

Currently we convert the user settings to PMSCR config in
arm_spe_event_to_pmscr() and set/clear the PMSCR register
separately. It blocks further extension for filtering the
exception level. So Factor out PMSCR set/clear operatons
into separate function and only configure the ELx filtering
when setting the register.

Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
 drivers/perf/arm_spe_pmu.c | 31 ++++++++++++++++++++++---------
 1 file changed, 22 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index 05647cfff61d..09570d4d63cd 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -297,7 +297,7 @@  static const struct attribute_group *arm_spe_pmu_attr_groups[] = {
 	NULL,
 };
 
-/* Convert between user ABI and register values */
+/* Convert between user ABI and register values, except the exception control */
 static u64 arm_spe_event_to_pmscr(struct perf_event *event)
 {
 	struct perf_event_attr *attr = &event->attr;
@@ -307,16 +307,32 @@  static u64 arm_spe_event_to_pmscr(struct perf_event *event)
 	reg |= FIELD_PREP(PMSCR_EL1x_PA, ATTR_CFG_GET_FLD(attr, pa_enable));
 	reg |= FIELD_PREP(PMSCR_EL1x_PCT, ATTR_CFG_GET_FLD(attr, pct_enable));
 
+	if (get_spe_event_has_cx(event))
+		reg |= PMSCR_EL1x_CX;
+
+	return reg;
+}
+
+static void arm_spe_pmu_set_pmscr(struct perf_event *event)
+{
+	struct perf_event_attr *attr = &event->attr;
+	u64 reg = 0;
+
+	reg = arm_spe_event_to_pmscr(event);
 	if (!attr->exclude_user)
 		reg |= PMSCR_EL1x_E0SPE;
 
 	if (!attr->exclude_kernel)
 		reg |= PMSCR_EL1x_E1SPE;
 
-	if (get_spe_event_has_cx(event))
-		reg |= PMSCR_EL1x_CX;
+	isb();
+	write_sysreg_s(reg, SYS_PMSCR_EL1);
+}
 
-	return reg;
+static void arm_spe_pmu_clr_pmscr(void)
+{
+	write_sysreg_s(0, SYS_PMSCR_EL1);
+	isb();
 }
 
 static void arm_spe_event_sanitise_period(struct perf_event *event)
@@ -566,8 +582,7 @@  static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle)
 static void arm_spe_pmu_disable_and_drain_local(void)
 {
 	/* Disable profiling at EL0 and EL1 */
-	write_sysreg_s(0, SYS_PMSCR_EL1);
-	isb();
+	arm_spe_pmu_clr_pmscr();
 
 	/* Drain any buffered data */
 	psb_csync();
@@ -808,9 +823,7 @@  static void arm_spe_pmu_start(struct perf_event *event, int flags)
 		write_sysreg_s(reg, SYS_PMSICR_EL1);
 	}
 
-	reg = arm_spe_event_to_pmscr(event);
-	isb();
-	write_sysreg_s(reg, SYS_PMSCR_EL1);
+	arm_spe_pmu_set_pmscr(event);
 }
 
 static void arm_spe_pmu_stop(struct perf_event *event, int flags)