[3/3] perf: arm_spe: Enable the profiling of EL0&1 translation regime

Commit Message

Yicong Yang Nov. 22, 2023, 8:46 a.m. UTC

From: Yicong Yang <[e-mail]>

On a VHE enabled host, the PMSCR_EL1 will be redirect to PMSCR_EL2
and we're actually enabling E0SPE and E2SPE in the driver. This means
the data from EL0&1 translation regime of a VM will not be profiled.
So this patch tries to add the support of profiling EL0 and EL1 of
a VM. Users can filter data of different exception level by using
the perf's exclude_* attributes. The exclude_* decision is referred
to Documentation/arch/arm64/perf.rst and the implementation of
arm_pmuv3.

Signed-off-by: Yicong Yang <[e-mail]>
---
 drivers/perf/arm_spe_pmu.c | 37 ++++++++++++++++++++++++++++++-------
 1 file changed, 30 insertions(+), 7 deletions(-)

Patch

diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index 09570d4d63cd..a647d625f359 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -316,21 +316,44 @@  static u64 arm_spe_event_to_pmscr(struct perf_event *event)
 static void arm_spe_pmu_set_pmscr(struct perf_event *event)
 {
 	struct perf_event_attr *attr = &event->attr;
-	u64 reg = 0;
+	u64 pmscr_el1, pmscr_el12;
 
-	reg = arm_spe_event_to_pmscr(event);
-	if (!attr->exclude_user)
-		reg |= PMSCR_EL1x_E0SPE;
+	pmscr_el1 = pmscr_el12 = arm_spe_event_to_pmscr(event);
+
+	/*
+	 * Map the exclude_* descision to ELx according to
+	 * Documentation/arch/arm64/perf.rst.
+	 */
+	if (is_kernel_in_hyp_mode()) {
+		if (!attr->exclude_kernel && !attr->exclude_host)
+			pmscr_el1 |= PMSCR_EL1x_E1SPE;
 
-	if (!attr->exclude_kernel)
-		reg |= PMSCR_EL1x_E1SPE;
+		if (!attr->exclude_kernel && !attr->exclude_guest)
+			pmscr_el12 |= PMSCR_EL1x_E1SPE;
+
+		if (!attr->exclude_user && !attr->exclude_host) {
+			pmscr_el1 |= PMSCR_EL1x_E0SPE;
+			pmscr_el12 |= PMSCR_EL1x_E0SPE;
+		}
+	} else {
+		if (!attr->exclude_kernel)
+			pmscr_el1 |= PMSCR_EL1x_E1SPE;
+
+		if (!attr->exclude_user)
+			pmscr_el1 |= PMSCR_EL1x_E0SPE;
+	}
 
 	isb();
-	write_sysreg_s(reg, SYS_PMSCR_EL1);
+	write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1);
+	if (is_kernel_in_hyp_mode())
+		write_sysreg_s(pmscr_el12, SYS_PMSCR_EL12);
 }
 
 static void arm_spe_pmu_clr_pmscr(void)
 {
+	if (is_kernel_in_hyp_mode())
+		write_sysreg_s(0, SYS_PMSCR_EL12);
+
 	write_sysreg_s(0, SYS_PMSCR_EL1);
 	isb();
 }