From patchwork Wed Nov 22 08:46:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13464240 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94E47C61D92 for ; Wed, 22 Nov 2023 08:49:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=stzEIfoYF/xs5GnAwAdrFV+gbDDKEivWiHMy7cXhv2w=; b=rHnVfesVFlQZi/ cUn0OUhZQC3krjRUxiC/dTvM8w0bhQscErhWz9tWynMJsBBwcljdNt8qWvzMhOYtzEQNOxFBGn0R6 gVIT3MkUfLFDbZ4n8JGAyQDOro/g0A2SA0s9ekLbYrInkdzXwCTL8q5jA9nH7WKc5FU6xo2QoK698 Il4rV4r98gVfFYx8FcsDwAMNEo95JoYaVEPCfrtCHXh7I3iAUtT28z80uoTHSZ82s3ZlRahcMRZ62 d2A6vt39bdAexwWatOBTKF2zqqilzSCfnBBp15cPPGOPA6nTFidk0r9Nlp5LVMJHX5z3uucjOeFbk 93QKa4C1rIKmD0TFFXtQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r5ivT-0016Sq-0a; Wed, 22 Nov 2023 08:49:39 +0000 Received: from szxga03-in.huawei.com ([45.249.212.189]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r5ivJ-0016Ps-29 for linux-arm-kernel@lists.infradead.org; Wed, 22 Nov 2023 08:49:31 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.55]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4SZvts2pB9zMnFQ; Wed, 22 Nov 2023 16:44:37 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 22 Nov 2023 16:49:20 +0800 From: Yicong Yang To: , , , , , , CC: , , , , , Subject: [PATCH 3/3] perf: arm_spe: Enable the profiling of EL0&1 translation regime Date: Wed, 22 Nov 2023 16:46:02 +0800 Message-ID: <20231122084602.53914-4-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231122084602.53914-1-yangyicong@huawei.com> References: <20231122084602.53914-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231122_004929_884939_B2D40AAD X-CRM114-Status: GOOD ( 13.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang On a VHE enabled host, the PMSCR_EL1 will be redirect to PMSCR_EL2 and we're actually enabling E0SPE and E2SPE in the driver. This means the data from EL0&1 translation regime of a VM will not be profiled. So this patch tries to add the support of profiling EL0 and EL1 of a VM. Users can filter data of different exception level by using the perf's exclude_* attributes. The exclude_* decision is referred to Documentation/arch/arm64/perf.rst and the implementation of arm_pmuv3. Signed-off-by: Yicong Yang --- drivers/perf/arm_spe_pmu.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 09570d4d63cd..a647d625f359 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -316,21 +316,44 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) static void arm_spe_pmu_set_pmscr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; - u64 reg = 0; + u64 pmscr_el1, pmscr_el12; - reg = arm_spe_event_to_pmscr(event); - if (!attr->exclude_user) - reg |= PMSCR_EL1x_E0SPE; + pmscr_el1 = pmscr_el12 = arm_spe_event_to_pmscr(event); + + /* + * Map the exclude_* descision to ELx according to + * Documentation/arch/arm64/perf.rst. + */ + if (is_kernel_in_hyp_mode()) { + if (!attr->exclude_kernel && !attr->exclude_host) + pmscr_el1 |= PMSCR_EL1x_E1SPE; - if (!attr->exclude_kernel) - reg |= PMSCR_EL1x_E1SPE; + if (!attr->exclude_kernel && !attr->exclude_guest) + pmscr_el12 |= PMSCR_EL1x_E1SPE; + + if (!attr->exclude_user && !attr->exclude_host) { + pmscr_el1 |= PMSCR_EL1x_E0SPE; + pmscr_el12 |= PMSCR_EL1x_E0SPE; + } + } else { + if (!attr->exclude_kernel) + pmscr_el1 |= PMSCR_EL1x_E1SPE; + + if (!attr->exclude_user) + pmscr_el1 |= PMSCR_EL1x_E0SPE; + } isb(); - write_sysreg_s(reg, SYS_PMSCR_EL1); + write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1); + if (is_kernel_in_hyp_mode()) + write_sysreg_s(pmscr_el12, SYS_PMSCR_EL12); } static void arm_spe_pmu_clr_pmscr(void) { + if (is_kernel_in_hyp_mode()) + write_sysreg_s(0, SYS_PMSCR_EL12); + write_sysreg_s(0, SYS_PMSCR_EL1); isb(); }