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Sat, 25 Nov 2023 06:40:47 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a208:d471:6d33:4b36:d85]) by smtp.gmail.com with ESMTPSA id h15-20020a17090aea8f00b002802d264240sm4817998pjz.29.2023.11.25.06.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 06:40:47 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Jagan Teki Subject: [PATCH 07/10] arm64: dts: rockchip: Add Edgeble NCM6A-IO M.2 M-Key Date: Sat, 25 Nov 2023 20:10:09 +0530 Message-Id: <20231125144012.58668-8-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231125144012.58668-1-jagan@edgeble.ai> References: <20231125144012.58668-1-jagan@edgeble.ai> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231125_064049_789153_EE6B5415 X-CRM114-Status: GOOD ( 11.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Edgeble NCM6A-IO board has M.2 M-Key via PCI3x4. Add support for it. Signed-off-by: Jagan Teki --- .../dts/rockchip/rk3588-edgeble-neu6a-io.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi index 7e838d76fa73..03a81f1dedf9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -22,6 +22,19 @@ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { startup-delay-us = <5000>; vin-supply = <&vcc_3v3_s3>; }; + + vcc3v3_pcie3x4: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_vcc3v3_en>; + regulator-name = "vcc3v3_pcie3x4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; }; &combphy0_ps { @@ -57,6 +70,19 @@ &pcie2x1l0 { status = "okay"; }; +&pcie30phy { + status = "okay"; +}; + +/* M-Key */ +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_rst>; + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */ + vpcie3v3-supply = <&vcc3v3_pcie3x4>; + status = "okay"; +}; + &pinctrl { pcie2 { pcie2_0_rst: pcie2-0-rst { @@ -64,6 +90,16 @@ pcie2_0_rst: pcie2-0-rst { }; }; + pcie3 { + pcie3x4_rst: pcie3x4-rst { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_vcc3v3_en: pcie3x4-vcc3v3-en { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;