diff mbox series

[2/7] arm64: dts: ti: k3-am69-sk: Enable Wave5 Video Encoder/Decoder

Message ID 20231127223718.2651185-3-b-brnich@ti.com (mailing list archive)
State New, archived
Headers show
Series Add Support for Wave5 on TI Devices | expand

Commit Message

Brandon Brnich Nov. 27, 2023, 10:37 p.m. UTC 
Update status for both Wave5 VPUs on AM69.

Wave521cl needs to use CMA as there is no IO MMU on AM69. Each
1080p channel requires roughly 98-100 MB. Allocate 1792 MB to meet 16
channel capability for AM69.

Signed-off-by: Brandon Brnich <b-brnich@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am69-sk.dts | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
index 9868c7049bfb..68ebdfe0ffc3 100644
--- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
@@ -43,6 +43,14 @@  reserved_memory: reserved-memory {
 		#size-cells = <2>;
 		ranges;
 
+		/* global cma region */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x00 0x70000000>;
+			linux,cma-default;
+		};
+
 		secure_ddr: optee@9e800000 {
 			reg = <0x00 0x9e800000 0x00 0x01800000>;
 			no-map;
@@ -706,6 +714,14 @@  &main_gpio0 {
 	pinctrl-0 = <&rpi_header_gpio0_pins_default>;
 };
 
+&vpu0 {
+	status = "okay";
+};
+
+&vpu1 {
+	status = "okay";
+};
+
 &mcu_cpsw {
 	status = "okay";
 	pinctrl-names = "default";