diff mbox series

[v2,1/3] arm64/sysreg: Add PMSCR_EL12 and factor out the common fields

Message ID 20231130074609.58668-2-yangyicong@huawei.com (mailing list archive)
State New, archived
Headers show
Series Enable the profiling of EL0&1 translation regime of ARM SPE | expand

Commit Message

Yicong Yang Nov. 30, 2023, 7:46 a.m. UTC 
From: Yicong Yang <yangyicong@hisilicon.com>

Add PMSCR_EL12 for accessing PMSCR_EL1 from EL2. Since PMSCR_EL12
and PMSCR_EL1 share the same definition of the fields, define a
common PMSCR_EL1x for both. Update the field name used in the
driver accordingly.

Trying hard to order PMSCR_EL12 by the address with its *_EL12
siblings in sysreg file.

Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/tools/sysreg    | 10 +++++++++-
 drivers/perf/arm_spe_pmu.c | 20 ++++++++++----------
 2 files changed, 19 insertions(+), 11 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 96cbeeab4eec..b55544f721ec 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1800,7 +1800,7 @@  Sysreg	FAR_EL1	3	0	6	0	0
 Field	63:0	ADDR
 EndSysreg
 
-Sysreg	PMSCR_EL1	3	0	9	9	0
+SysregFields	PMSCR_EL1x
 Res0	63:8
 Field	7:6	PCT
 Field	5	TS
@@ -1809,6 +1809,10 @@  Field	3	CX
 Res0	2
 Field	1	E1SPE
 Field	0	E0SPE
+EndSysregFields
+
+Sysreg	PMSCR_EL1	3	0	9	9	0
+Fields	PMSCR_EL1x
 EndSysreg
 
 Sysreg	PMSNEVFR_EL1	3	0	9	9	1
@@ -2411,6 +2415,10 @@  Sysreg	FAR_EL12	3	5	6	0	0
 Field	63:0	ADDR
 EndSysreg
 
+Sysreg	PMSCR_EL12	3	5	9	9	0
+Fields	PMSCR_EL1x
+EndSysreg
+
 Sysreg	CONTEXTIDR_EL12	3	5	13	0	1
 Fields	CONTEXTIDR_ELx
 EndSysreg
diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c
index d2b0cbf0e0c4..05647cfff61d 100644
--- a/drivers/perf/arm_spe_pmu.c
+++ b/drivers/perf/arm_spe_pmu.c
@@ -172,13 +172,13 @@  static const struct attribute_group arm_spe_pmu_cap_group = {
 };
 
 /* User ABI */
-#define ATTR_CFG_FLD_ts_enable_CFG		config	/* PMSCR_EL1.TS */
+#define ATTR_CFG_FLD_ts_enable_CFG		config	/* PMSCR_EL1x.TS */
 #define ATTR_CFG_FLD_ts_enable_LO		0
 #define ATTR_CFG_FLD_ts_enable_HI		0
-#define ATTR_CFG_FLD_pa_enable_CFG		config	/* PMSCR_EL1.PA */
+#define ATTR_CFG_FLD_pa_enable_CFG		config	/* PMSCR_EL1x.PA */
 #define ATTR_CFG_FLD_pa_enable_LO		1
 #define ATTR_CFG_FLD_pa_enable_HI		1
-#define ATTR_CFG_FLD_pct_enable_CFG		config	/* PMSCR_EL1.PCT */
+#define ATTR_CFG_FLD_pct_enable_CFG		config	/* PMSCR_EL1x.PCT */
 #define ATTR_CFG_FLD_pct_enable_LO		2
 #define ATTR_CFG_FLD_pct_enable_HI		2
 #define ATTR_CFG_FLD_jitter_CFG			config	/* PMSIRR_EL1.RND */
@@ -303,18 +303,18 @@  static u64 arm_spe_event_to_pmscr(struct perf_event *event)
 	struct perf_event_attr *attr = &event->attr;
 	u64 reg = 0;
 
-	reg |= FIELD_PREP(PMSCR_EL1_TS, ATTR_CFG_GET_FLD(attr, ts_enable));
-	reg |= FIELD_PREP(PMSCR_EL1_PA, ATTR_CFG_GET_FLD(attr, pa_enable));
-	reg |= FIELD_PREP(PMSCR_EL1_PCT, ATTR_CFG_GET_FLD(attr, pct_enable));
+	reg |= FIELD_PREP(PMSCR_EL1x_TS, ATTR_CFG_GET_FLD(attr, ts_enable));
+	reg |= FIELD_PREP(PMSCR_EL1x_PA, ATTR_CFG_GET_FLD(attr, pa_enable));
+	reg |= FIELD_PREP(PMSCR_EL1x_PCT, ATTR_CFG_GET_FLD(attr, pct_enable));
 
 	if (!attr->exclude_user)
-		reg |= PMSCR_EL1_E0SPE;
+		reg |= PMSCR_EL1x_E0SPE;
 
 	if (!attr->exclude_kernel)
-		reg |= PMSCR_EL1_E1SPE;
+		reg |= PMSCR_EL1x_E1SPE;
 
 	if (get_spe_event_has_cx(event))
-		reg |= PMSCR_EL1_CX;
+		reg |= PMSCR_EL1x_CX;
 
 	return reg;
 }
@@ -768,7 +768,7 @@  static int arm_spe_pmu_event_init(struct perf_event *event)
 	set_spe_event_has_cx(event);
 	reg = arm_spe_event_to_pmscr(event);
 	if (!perfmon_capable() &&
-	    (reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT)))
+	    (reg & (PMSCR_EL1x_PA | PMSCR_EL1x_PCT)))
 		return -EACCES;
 
 	return 0;