From patchwork Thu Nov 30 07:46:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13474127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 14098C10DC2 for ; Thu, 30 Nov 2023 07:50:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6TcI4G1p9JSJ1DrUL6M3qNEh0VlETKHwLfqw4CVIK2Q=; b=bIN5fSceaiDlJU i/bWEwegCl9J2SGBkBm8MV076cGRpcr40Vld2B24lbufjmyKje7iou1aurJ9o0k5wzQ8F5qW3AYAT VFYIQk7/cL3MIEFvvP3qNUS6+xHfwt8EaqBSA5Upka5pnZgkHgY1s3oo5dsiC2YVBpoYgXFSRKrQY JfcxecgrBLVwkNoC+Rq29st5EA/U0xY1oq7C0AFb1cgwNK1k2QaDTbBKSI9Zp6uimo5eFmHBRKlot /2wUPaWZfahzmyGjRsz2nVRGNuB4dOFhpez3Zbqzsb6vStHCNtxBO2DrvEKEMj9Ji86AMc6HgZfXZ 6KUaUFWYsfkMnHys8PJA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r8bnx-00A8Cr-1Z; Thu, 30 Nov 2023 07:49:49 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r8bnn-00A88n-01 for linux-arm-kernel@lists.infradead.org; Thu, 30 Nov 2023 07:49:40 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4SgpH070lzzvRLt; Thu, 30 Nov 2023 15:49:00 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Nov 2023 15:49:33 +0800 From: Yicong Yang To: , , , , , , CC: , , , , , Subject: [PATCH v2 1/3] arm64/sysreg: Add PMSCR_EL12 and factor out the common fields Date: Thu, 30 Nov 2023 15:46:07 +0800 Message-ID: <20231130074609.58668-2-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231130074609.58668-1-yangyicong@huawei.com> References: <20231130074609.58668-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231129_234939_364297_9094F884 X-CRM114-Status: GOOD ( 13.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang Add PMSCR_EL12 for accessing PMSCR_EL1 from EL2. Since PMSCR_EL12 and PMSCR_EL1 share the same definition of the fields, define a common PMSCR_EL1x for both. Update the field name used in the driver accordingly. Trying hard to order PMSCR_EL12 by the address with its *_EL12 siblings in sysreg file. Signed-off-by: Yicong Yang Reviewed-by: Mark Brown --- arch/arm64/tools/sysreg | 10 +++++++++- drivers/perf/arm_spe_pmu.c | 20 ++++++++++---------- 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 96cbeeab4eec..b55544f721ec 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1800,7 +1800,7 @@ Sysreg FAR_EL1 3 0 6 0 0 Field 63:0 ADDR EndSysreg -Sysreg PMSCR_EL1 3 0 9 9 0 +SysregFields PMSCR_EL1x Res0 63:8 Field 7:6 PCT Field 5 TS @@ -1809,6 +1809,10 @@ Field 3 CX Res0 2 Field 1 E1SPE Field 0 E0SPE +EndSysregFields + +Sysreg PMSCR_EL1 3 0 9 9 0 +Fields PMSCR_EL1x EndSysreg Sysreg PMSNEVFR_EL1 3 0 9 9 1 @@ -2411,6 +2415,10 @@ Sysreg FAR_EL12 3 5 6 0 0 Field 63:0 ADDR EndSysreg +Sysreg PMSCR_EL12 3 5 9 9 0 +Fields PMSCR_EL1x +EndSysreg + Sysreg CONTEXTIDR_EL12 3 5 13 0 1 Fields CONTEXTIDR_ELx EndSysreg diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index d2b0cbf0e0c4..05647cfff61d 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -172,13 +172,13 @@ static const struct attribute_group arm_spe_pmu_cap_group = { }; /* User ABI */ -#define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1.TS */ +#define ATTR_CFG_FLD_ts_enable_CFG config /* PMSCR_EL1x.TS */ #define ATTR_CFG_FLD_ts_enable_LO 0 #define ATTR_CFG_FLD_ts_enable_HI 0 -#define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1.PA */ +#define ATTR_CFG_FLD_pa_enable_CFG config /* PMSCR_EL1x.PA */ #define ATTR_CFG_FLD_pa_enable_LO 1 #define ATTR_CFG_FLD_pa_enable_HI 1 -#define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1.PCT */ +#define ATTR_CFG_FLD_pct_enable_CFG config /* PMSCR_EL1x.PCT */ #define ATTR_CFG_FLD_pct_enable_LO 2 #define ATTR_CFG_FLD_pct_enable_HI 2 #define ATTR_CFG_FLD_jitter_CFG config /* PMSIRR_EL1.RND */ @@ -303,18 +303,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= FIELD_PREP(PMSCR_EL1_TS, ATTR_CFG_GET_FLD(attr, ts_enable)); - reg |= FIELD_PREP(PMSCR_EL1_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); - reg |= FIELD_PREP(PMSCR_EL1_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); + reg |= FIELD_PREP(PMSCR_EL1x_TS, ATTR_CFG_GET_FLD(attr, ts_enable)); + reg |= FIELD_PREP(PMSCR_EL1x_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); + reg |= FIELD_PREP(PMSCR_EL1x_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); if (!attr->exclude_user) - reg |= PMSCR_EL1_E0SPE; + reg |= PMSCR_EL1x_E0SPE; if (!attr->exclude_kernel) - reg |= PMSCR_EL1_E1SPE; + reg |= PMSCR_EL1x_E1SPE; if (get_spe_event_has_cx(event)) - reg |= PMSCR_EL1_CX; + reg |= PMSCR_EL1x_CX; return reg; } @@ -768,7 +768,7 @@ static int arm_spe_pmu_event_init(struct perf_event *event) set_spe_event_has_cx(event); reg = arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT))) + (reg & (PMSCR_EL1x_PA | PMSCR_EL1x_PCT))) return -EACCES; return 0;