From patchwork Thu Nov 30 07:46:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 13474129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A8BCCC4167B for ; Thu, 30 Nov 2023 07:50:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MQMtQVyYjYMeGvDB/YM051aCONi0wYJ1njcWq4yJyPo=; b=2ufCs9AZAyiqi6 6/78ntL+wv+X0+F5AbiAIGivSLSN9CS332kf1J2KmwznCCztWLDQgfwPUSgyIQEd+1yYG2mJJHf6Z Qso90QipD+3eefC3RWL3xjGE2e58xkp85jCNIUXNpHrA7rQZFMitrCPPj46ZktcYT7nOaxVcAP0Ug lBS1zEer+epmVLBrk+n+t8dcrsl6iWWfuzr39sgdox/FM/GwiiW/zNxxTPdhT08Poi9vuXUA+qBUR ch4UzQGWpf4+VVxP5ZqNLhp3xf71q7DYxOnzPBQedMqRrfvENqHkszQxr8bQ2GomWmAFG5cZuqlsK qsSCxvylLZbkHHIFLPmw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r8bnw-00A8CU-33; Thu, 30 Nov 2023 07:49:48 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r8bnm-00A88m-3C for linux-arm-kernel@lists.infradead.org; Thu, 30 Nov 2023 07:49:40 +0000 Received: from canpemm500009.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4SgpH06ScZzvRCs; Thu, 30 Nov 2023 15:49:00 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 30 Nov 2023 15:49:33 +0800 From: Yicong Yang To: , , , , , , CC: , , , , , Subject: [PATCH v2 2/3] perf: arm_spe: Factor out PMSCR set/clear operations Date: Thu, 30 Nov 2023 15:46:08 +0800 Message-ID: <20231130074609.58668-3-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20231130074609.58668-1-yangyicong@huawei.com> References: <20231130074609.58668-1-yangyicong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231129_234939_350520_01107B4C X-CRM114-Status: GOOD ( 12.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Yicong Yang Currently we convert the user settings to PMSCR config in arm_spe_event_to_pmscr() and set/clear the PMSCR register separately. It blocks further extension for filtering the exception level. So Factor out PMSCR set/clear operatons into separate function and only configure the ELx filtering when setting the register. Signed-off-by: Yicong Yang --- drivers/perf/arm_spe_pmu.c | 31 ++++++++++++++++++++++--------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 05647cfff61d..09570d4d63cd 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -297,7 +297,7 @@ static const struct attribute_group *arm_spe_pmu_attr_groups[] = { NULL, }; -/* Convert between user ABI and register values */ +/* Convert between user ABI and register values, except the exception control */ static u64 arm_spe_event_to_pmscr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; @@ -307,16 +307,32 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) reg |= FIELD_PREP(PMSCR_EL1x_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); reg |= FIELD_PREP(PMSCR_EL1x_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); + if (get_spe_event_has_cx(event)) + reg |= PMSCR_EL1x_CX; + + return reg; +} + +static void arm_spe_pmu_set_pmscr(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + u64 reg = 0; + + reg = arm_spe_event_to_pmscr(event); if (!attr->exclude_user) reg |= PMSCR_EL1x_E0SPE; if (!attr->exclude_kernel) reg |= PMSCR_EL1x_E1SPE; - if (get_spe_event_has_cx(event)) - reg |= PMSCR_EL1x_CX; + isb(); + write_sysreg_s(reg, SYS_PMSCR_EL1); +} - return reg; +static void arm_spe_pmu_clr_pmscr(void) +{ + write_sysreg_s(0, SYS_PMSCR_EL1); + isb(); } static void arm_spe_event_sanitise_period(struct perf_event *event) @@ -566,8 +582,7 @@ static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle) static void arm_spe_pmu_disable_and_drain_local(void) { /* Disable profiling at EL0 and EL1 */ - write_sysreg_s(0, SYS_PMSCR_EL1); - isb(); + arm_spe_pmu_clr_pmscr(); /* Drain any buffered data */ psb_csync(); @@ -808,9 +823,7 @@ static void arm_spe_pmu_start(struct perf_event *event, int flags) write_sysreg_s(reg, SYS_PMSICR_EL1); } - reg = arm_spe_event_to_pmscr(event); - isb(); - write_sysreg_s(reg, SYS_PMSCR_EL1); + arm_spe_pmu_set_pmscr(event); } static void arm_spe_pmu_stop(struct perf_event *event, int flags)