From patchwork Fri Dec 1 16:09:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 13476055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33751C4167B for ; Fri, 1 Dec 2023 16:11:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ZR+3Odjk6qXfCS6rGk3xTrcTIOSi7/aQIXmAWiO78kI=; b=cPjPIhiFa9MSbX p2gOEaJ04XVPhdmyTea38uIkptB3tL62KidohVou0+zsAi7WWeuGeCspgbnUvzW9pG1yDx86QTbEM EULXdEsFmRRY5JW0/Rf+g/XXqWkBAp65Zw1kqDeZyHOmCLewZ+hRxTZq76oy8MOP4xS4co+kDhgsq gVmoXPv/tmvJoj3gcsUEMR3xEAoYH/d/NBl8JOLkh3HKpoZvW+5aVkz6ux02vvjn6jW876WfF9A0/ 2ENuLNUhd1NqOCdLyt66g/cAl5U5FaJtNjvPQooSqmPQn0Fkbcgs7BaIYd+JuNOJwpqiltdvvB+ll brzFD3R3auRGyxt+ytdw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r966u-00E88l-2J; Fri, 01 Dec 2023 16:11:24 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r966l-00E7zJ-1H for linux-arm-kernel@lists.infradead.org; Fri, 01 Dec 2023 16:11:19 +0000 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-33332096330so466642f8f.1 for ; Fri, 01 Dec 2023 08:11:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701447074; x=1702051874; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aaU+AouooGnkGzWi0PzU+0h34M8EDB8UlNICIdkMRds=; b=L3/Tx/nbMYMCXza9GYgLTCc9pXyWicfgPvM4VIUFlAYxVShITWmtWi/HvU9yxNxR59 eo0AjTpCB6C5DhMt1HsCBdcu2Kpj5/WQ9I+iWpPU2fMJg2ftgbkxSNvWkQ/tatbbUT4N gx3Q9I/mZBILZFxzPSQO0m91sX57joA2v4Rot+SyQ/IiBwAsyOXFOQMT/IYA3HZlmT0l ZL1iecm4oewnsrzK1EvjudN8TZIz6gHEPNY0WHh+jG0dqSNeQNhpz3G16r+ciNJOCYv6 w5b7UIEPv0ADcQ1leGyW1DUTy4EV2BYBEC8l2KtYe2MB78RFmIBpc5YcDxa3STpyuaua s4Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701447074; x=1702051874; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aaU+AouooGnkGzWi0PzU+0h34M8EDB8UlNICIdkMRds=; b=RSXR54Ljd/9uPlwKZEsRoICZ1G3nE+CgV4KvKJcp8nKWtMXt8ZUefhQ5JwcuNNBs/6 WOl9gypg0wQXHUbdyB+qKca3Sry7ONohOi1V3Jf8YWsyOWmqznuRkf45oISewyoGCyGB 7gOoNTweXWSG5a5Y8ZOicSI0qgsB1RPnU7YYbDDwviT/AcB848prwfpDAqL5KdFffe4I tvgzzTvoZBVp6iBKAird1m7BvD0Fn/8wwE2jm5L/ni/iqCbprDWfMyHRo7sNNq4L5Bny 4hAc4H3m2mqFeOvzXvu3+X4KTznKv3nKkUjTOL73GGL6o7iK7uTAaCzbpix6WPS0/qmc xIrA== X-Gm-Message-State: AOJu0YyTCt8g+/1FFl5FK3T2pINy/DshcUQo/XMvs1xtv42aENytwlSK +gSbZVqeQo75KBQQB46R9YTzHg== X-Google-Smtp-Source: AGHT+IHuelNBPqYMtuGM8bHOu2LSauHdS8e/DXbd8w0Q2267R40LFMPAsMWXtWSv22eoArxADa6lgw== X-Received: by 2002:adf:f1cb:0:b0:333:2fd7:95ea with SMTP id z11-20020adff1cb000000b003332fd795eamr873370wro.37.1701447074095; Fri, 01 Dec 2023 08:11:14 -0800 (PST) Received: from gpeter-l.lan (host-92-29-24-243.as13285.net. [92.29.24.243]) by smtp.gmail.com with ESMTPSA id cg16-20020a5d5cd0000000b003332656cd73sm3907386wrb.105.2023.12.01.08.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Dec 2023 08:11:13 -0800 (PST) From: Peter Griffin To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, jirislaby@kernel.org, cw00.choi@samsung.com, alim.akhtar@samsung.com Cc: peter.griffin@linaro.org, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: [PATCH v5 16/20] watchdog: s3c2410_wdt: Add support for Google gs101 SoC Date: Fri, 1 Dec 2023 16:09:21 +0000 Message-ID: <20231201160925.3136868-17-peter.griffin@linaro.org> X-Mailer: git-send-email 2.43.0.rc2.451.g8631bc7472-goog In-Reply-To: <20231201160925.3136868-1-peter.griffin@linaro.org> References: <20231201160925.3136868-1-peter.griffin@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231201_081115_450953_03796533 X-CRM114-Status: GOOD ( 14.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds the compatibles and drvdata for the Google gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones. Similar to Exynos850 it has two watchdog instances, one for each cluster and has some control bits in PMU registers. gs101 also has the dbgack_mask bit in wtcon register, so we also enable QUIRK_HAS_DBGACK_BIT. Signed-off-by: Peter Griffin Tested-by: Will McVicker Reviewed-by: Sam Protsenko --- drivers/watchdog/s3c2410_wdt.c | 47 ++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 39f3489e41d6..c1ae71574457 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -68,6 +68,13 @@ #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24 +#define GS_CLUSTER0_NONCPU_OUT 0x1220 +#define GS_CLUSTER1_NONCPU_OUT 0x1420 +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244 +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444 +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644 +#define GS_RST_STAT_REG_OFFSET 0x3B44 + /** * DOC: Quirk flags for different Samsung watchdog IP-cores * @@ -269,6 +276,30 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = { QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, }; +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = { + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN, + .mask_bit = 2, + .mask_reset_inv = true, + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, + .rst_stat_bit = 0, + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT, + .cnt_en_bit = 8, + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT, +}; + +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = { + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN, + .mask_bit = 2, + .mask_reset_inv = true, + .rst_stat_reg = GS_RST_STAT_REG_OFFSET, + .rst_stat_bit = 1, + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT, + .cnt_en_bit = 7, + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN | + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT, +}; + static const struct of_device_id s3c2410_wdt_match[] = { { .compatible = "samsung,s3c2410-wdt", .data = &drv_data_s3c2410 }, @@ -284,6 +315,8 @@ static const struct of_device_id s3c2410_wdt_match[] = { .data = &drv_data_exynos850_cl0 }, { .compatible = "samsung,exynosautov9-wdt", .data = &drv_data_exynosautov9_cl0 }, + { .compatible = "google,gs101-wdt", + .data = &drv_data_gs101_cl0 }, {}, }; MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); @@ -604,9 +637,10 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) } #ifdef CONFIG_OF - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ + /* Choose Exynos850/ExynosAutov9/gs101 driver data w.r.t. cluster index */ if (variant == &drv_data_exynos850_cl0 || - variant == &drv_data_exynosautov9_cl0) { + variant == &drv_data_exynosautov9_cl0 || + variant == &drv_data_gs101_cl0) { u32 index; int err; @@ -619,9 +653,12 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt) case 0: break; case 1: - variant = (variant == &drv_data_exynos850_cl0) ? - &drv_data_exynos850_cl1 : - &drv_data_exynosautov9_cl1; + if (variant == &drv_data_exynos850_cl0) + variant = &drv_data_exynos850_cl1; + else if (variant == &drv_data_exynosautov9_cl0) + variant = &drv_data_exynosautov9_cl1; + else if (variant == &drv_data_gs101_cl0) + variant = &drv_data_gs101_cl1; break; default: return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);