From patchwork Sat Dec 2 08:50:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddharth Vadapalli X-Patchwork-Id: 13476816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F701C4167B for ; Sat, 2 Dec 2023 08:50:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=wBKFEvlaXgbn3PCGpqXxJ5xQpE15adMUGMJ4q4Au0kk=; b=M860n8sxZhO8L8 gCEaj8T77cM7Wqi+w+p/IVZBuksXVSpWNwecPDatyT+ag6GnFFV48ruj1oy7Xgi95+OC0S2KjrLxX 93FSPp8FFCRuUCiHKoaU7vZOp7vT0eGwMh3mgiKWQcWySIAwKfGCf3Mc9FKRYG808XSE6MHXUgXY6 IykbfxhElwfIRNgrCg1L4cB9IgmqOd+h54olKqeXLPPGVq6wKfLTAeunI98EmbJAb5pyFBLiIH82a EakSMfyC93IshjTaS6BNwCXu56+PykVxGVix/WYaknsa7Ju6SKw7HGxFInLjYiuPFEQGxl5v3Kx4W UNOu2V6jb18g0j/a3E+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r9Lht-00FKy5-0S; Sat, 02 Dec 2023 08:50:37 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r9Lhq-00FKxE-1x for linux-arm-kernel@lists.infradead.org; Sat, 02 Dec 2023 08:50:36 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3B28oJvO048633; Sat, 2 Dec 2023 02:50:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1701507019; bh=5eLMeR7O3XmgWYr3v/Y9HZ53t+c9lMwwKXavX+OjuwA=; h=From:To:CC:Subject:Date; b=uPnW9bc0vJAgRIKvDOPa9kPaxyHNisBdNDhx+Xt7hyEAl4H71vXLypp+pm3aol2TV kzGVOWxwUPF+Bx84qEFNSWr8R+FceRZkJNOc+1dasAv/tbsXuWRrIKk2TImFKRMcJq oJsNwMf45Ia4opPErFX6h131kWvLFVo9RfMKWtnE= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3B28oJE9002281 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 2 Dec 2023 02:50:19 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 2 Dec 2023 02:50:19 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 2 Dec 2023 02:50:19 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3B28oGEW067220; Sat, 2 Dec 2023 02:50:16 -0600 From: Siddharth Vadapalli To: , , , CC: , , , , , , Subject: [PATCH v4] PCI: Cadence: Clear the ARI Capability Next Function Number of the last function Date: Sat, 2 Dec 2023 14:20:15 +0530 Message-ID: <20231202085015.3048516-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231202_005034_771887_69AD66F4 X-CRM114-Status: GOOD ( 13.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jasko-EXT Wojciech Next Function Number field in ARI Capability Register for last function must be zero by default as per the PCIe specification, indicating there is no next higher number function but that's not happening in our case, so this patch clears the Next Function Number field for last function used. Signed-off-by: Jasko-EXT Wojciech Signed-off-by: Achal Verma Reviewed-by: Vignesh Raghavendra Signed-off-by: Siddharth Vadapalli --- Hello, This patch is based on linux-next tagged next-20231201. v3: https://patchwork.kernel.org/project/linux-pci/patch/20230316071156.200888-1-a-verma1@ti.com/ Changes since v3: - Rebased on next-20231201. - Collected Reviewed-by tag from Vignesh Raghavendra . Regards, Siddharth. drivers/pci/controller/cadence/pcie-cadence-ep.c | 14 +++++++++++++- drivers/pci/controller/cadence/pcie-cadence.h | 6 ++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index 3142feb8ac19..2dd4d7027659 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -566,7 +566,8 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) struct cdns_pcie *pcie = &ep->pcie; struct device *dev = pcie->dev; int max_epfs = sizeof(epc->function_num_map) * 8; - int ret, value, epf; + int ret, epf, last_fn; + u32 reg, value; /* * BIT(0) is hardwired to 1, hence function 0 is always enabled @@ -574,6 +575,17 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) */ cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, epc->function_num_map); + /* + * Next function field in ARI_CAP_AND_CTR register for last function + * should be 0. + * Clearing Next Function Number field for the last function used. + */ + last_fn = find_last_bit(&epc->function_num_map, BITS_PER_LONG); + reg = CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn); + value = cdns_pcie_readl(pcie, reg); + value &= ~CDNS_PCIE_ARI_CAP_NFN_MASK; + cdns_pcie_writel(pcie, reg, value); + if (ep->quirk_disable_flr) { for (epf = 0; epf < max_epfs; epf++) { if (!(epc->function_num_map & BIT(epf))) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 373cb50fcd15..9c16745582eb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -130,6 +130,12 @@ #define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 +/* + * Endpoint PF Registers + */ +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) + /* * Root Port Registers (PCI configuration space for the root port function) */