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Sat, 02 Dec 2023 04:42:08 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:908e:b829:354b:f8ee]) by smtp.gmail.com with ESMTPSA id q19-20020a1709060e5300b009a19701e7b5sm3009602eji.96.2023.12.02.04.42.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Dec 2023 04:42:08 -0800 (PST) From: Alex Bee To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alex Bee Subject: [PATCH v2 2/2] ARM: dts: rockchip: Enable gmac for XPI-3128 Date: Sat, 2 Dec 2023 13:41:59 +0100 Message-ID: <20231202124158.65615-4-knaerzche@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231202124158.65615-2-knaerzche@gmail.com> References: <20231202124158.65615-2-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231202_044217_771728_C649C013 X-CRM114-Status: GOOD ( 11.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the required properties and enable the gmac node for XPI-3128 board. The minimum reset timing requirements for the phy have been taken from DP83848J's datasheet [0] [0] https://www.ti.com/lit/ds/symlink/dp83848j.pdf Signed-off-by: Alex Bee --- .../arm/boot/dts/rockchip/rk3128-xpi-3128.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts index 61b9f069c8a2..e979425f11a0 100644 --- a/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts +++ b/arch/arm/boot/dts/rockchip/rk3128-xpi-3128.dts @@ -11,6 +11,7 @@ / { compatible = "geniatech,xpi-3128", "rockchip,rk3128"; aliases { + ethernet0 = &gmac; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; @@ -255,6 +256,18 @@ &emmc { status = "okay"; }; +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_lan>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + assigned-clocks = <&cru SCLK_MAC_SRC>; + assigned-clock-rates= <50000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + status = "okay"; +}; + &gpio0 { gpio-line-names = /* GPIO0 A0-A7 */ "", "", "HEADER_5", "HEADER_3", @@ -315,6 +328,21 @@ &gpio3 { "", "", "", ""; }; +&mdio { + phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + max-speed = <100>; + /* T2.2.4 min. 1 us */ + reset-assert-us = <10>; + /* T2.2.1 + T2.2.2 + T2.2.3 min. 6.05 us */ + reset-deassert-us = <20>; + reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&dp83848c_rst>; + }; +}; + &pinctrl { dp83848c { dp83848c_rst: dp83848c-rst {