| Message ID | 20231207081917.340167-3-danishanwar@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add AM64x ICSSG Ethernet support | expand |
On 13:49-20231207, MD Danish Anwar wrote: > ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded. > > The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares > MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to > CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO > bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2) > port is kept disable and ICSSG1 is enabled in single MAC mode by > default. > > Signed-off-by: MD Danish Anwar <danishanwar@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am642-evm.dts | 105 ++++++++++++++++++++++++ > 1 file changed, 105 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts > index 8c5651d2cf5d..04d1c0602d31 100644 > --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts > +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts > @@ -34,6 +34,11 @@ aliases { > ethernet1 = &cpsw_port2; > }; > > + aliases { > + ethernet2 = &icssg1_emac0; > + ethernet3 = &icssg1_emac1; > + }; Why another aliases section? > + > memory@80000000 { > bootph-all; > device_type = "memory"; > @@ -229,6 +234,70 @@ transceiver2: can-phy1 { > max-bitrate = <5000000>; > standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; > }; > + > + icssg1_eth: icssg1-eth { > + compatible = "ti,am642-icssg-prueth"; > + pinctrl-names = "default"; > + pinctrl-0 = <&icssg1_rgmii1_pins_default>; > + > + sram = <&oc_sram>; > + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; > + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", > + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", > + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", > + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", > + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", > + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; Umm... am65x??? is that a typo? I'd rather keep it am64x here and drop that sr2 thing. Tomorrow there will be a custom bug on am64 and then we will have to respin this again. > + > + ti,pruss-gp-mux-sel = <2>, /* MII mode */ > + <2>, > + <2>, > + <2>, /* MII mode */ > + <2>, > + <2>; > + > + ti,mii-g-rt = <&icssg1_mii_g_rt>; > + ti,mii-rt = <&icssg1_mii_rt>; > + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; > + > + interrupt-parent = <&icssg1_intc>; > + interrupts = <24 0 2>, <25 1 3>; > + interrupt-names = "tx_ts0", "tx_ts1"; > + > + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ > + <&main_pktdma 0xc201 15>, /* egress slice 0 */ > + <&main_pktdma 0xc202 15>, /* egress slice 0 */ > + <&main_pktdma 0xc203 15>, /* egress slice 0 */ > + <&main_pktdma 0xc204 15>, /* egress slice 1 */ > + <&main_pktdma 0xc205 15>, /* egress slice 1 */ > + <&main_pktdma 0xc206 15>, /* egress slice 1 */ > + <&main_pktdma 0xc207 15>, /* egress slice 1 */ > + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ > + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ > + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", > + "tx1-0", "tx1-1", "tx1-2", "tx1-3", > + "rx0", "rx1"; > + > + ethernet-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + icssg1_emac0: port@0 { > + reg = <0>; > + phy-handle = <&icssg1_phy1>; > + phy-mode = "rgmii-id"; > + ti,syscon-rgmii-delay = <&main_conf 0x4110>; > + /* Filled in by bootloader */ > + local-mac-address = [00 00 00 00 00 00]; > + }; > + icssg1_emac1: port@1 { > + reg = <1>; > + ti,syscon-rgmii-delay = <&main_conf 0x4114>; > + /* Filled in by bootloader */ > + local-mac-address = [00 00 00 00 00 00]; > + status = "disabled"; > + }; > + }; > + }; > }; > > &main_pmx0 { > @@ -383,6 +452,30 @@ ddr_vtt_pins_default: ddr-vtt-default-pins { > AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ > >; > }; > + > + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { > + pinctrl-single,pins = < > + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ > + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ > + >; > + }; > + > + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ > + pinctrl-single,pins = < > + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ > + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ > + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ > + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ > + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ > + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ > + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ > + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ > + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ > + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ > + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ > + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ > + >; > + }; > }; > > &main_uart0 { > @@ -731,3 +824,15 @@ &main_mcan1 { > pinctrl-0 = <&main_mcan1_pins_default>; > phys = <&transceiver2>; > }; > + > +&icssg1_mdio { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&icssg1_mdio1_pins_default>; > + > + icssg1_phy1: ethernet-phy@0 { > + reg = <0xf>; > + tx-internal-delay-ps = <250>; > + rx-internal-delay-ps = <2000>; > + }; > +}; > -- > 2.34.1 >
On 12/7/2023 6:48 PM, Nishanth Menon wrote: > On 13:49-20231207, MD Danish Anwar wrote: >> ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded. >> >> The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares >> MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to >> CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO >> bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2) >> port is kept disable and ICSSG1 is enabled in single MAC mode by >> default. >> >> Signed-off-by: MD Danish Anwar <danishanwar@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 105 ++++++++++++++++++++++++ >> 1 file changed, 105 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts >> index 8c5651d2cf5d..04d1c0602d31 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts >> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts >> @@ -34,6 +34,11 @@ aliases { >> ethernet1 = &cpsw_port2; >> }; >> >> + aliases { >> + ethernet2 = &icssg1_emac0; >> + ethernet3 = &icssg1_emac1; >> + }; > > Why another aliases section? > Sorry, My bad. I had created these patches a while back when there was no alias section in this dts file, and applied them directly here. I didn't notice the already existing alias section. I will remove this aliases section and move these two aliases two the above section in v2. >> + >> memory@80000000 { >> bootph-all; >> device_type = "memory"; >> @@ -229,6 +234,70 @@ transceiver2: can-phy1 { >> max-bitrate = <5000000>; >> standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; >> }; >> + >> + icssg1_eth: icssg1-eth { >> + compatible = "ti,am642-icssg-prueth"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&icssg1_rgmii1_pins_default>; >> + >> + sram = <&oc_sram>; >> + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; >> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", >> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", >> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", >> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", >> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", >> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; > > Umm... am65x??? is that a typo? I'd rather keep it am64x here and drop > that sr2 thing. Tomorrow there will be a custom bug on am64 and then we > will have to respin this again. > No Nishant, this is not a typo. Both AM64x and AM65x use the same ICSSG firmwares. We only have am65x-sr2-* firmwares and they are used by both AM64x and AM65x and that is why I have kept the firmware-name here in dt same as the files that we load on the pru cores. >> + >> + ti,pruss-gp-mux-sel = <2>, /* MII mode */ >> + <2>, >> + <2>, >> + <2>, /* MII mode */ >> + <2>, >> + <2>; >> + >> + ti,mii-g-rt = <&icssg1_mii_g_rt>; >> + ti,mii-rt = <&icssg1_mii_rt>; >> + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; >> + >> + interrupt-parent = <&icssg1_intc>; >> + interrupts = <24 0 2>, <25 1 3>; >> + interrupt-names = "tx_ts0", "tx_ts1"; >> + >> + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ >> + <&main_pktdma 0xc201 15>, /* egress slice 0 */ >> + <&main_pktdma 0xc202 15>, /* egress slice 0 */ >> + <&main_pktdma 0xc203 15>, /* egress slice 0 */ >> + <&main_pktdma 0xc204 15>, /* egress slice 1 */ >> + <&main_pktdma 0xc205 15>, /* egress slice 1 */ >> + <&main_pktdma 0xc206 15>, /* egress slice 1 */ >> + <&main_pktdma 0xc207 15>, /* egress slice 1 */ >> + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ >> + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ >> + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", >> + "tx1-0", "tx1-1", "tx1-2", "tx1-3", >> + "rx0", "rx1"; >> + >> + ethernet-ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + icssg1_emac0: port@0 { >> + reg = <0>; >> + phy-handle = <&icssg1_phy1>; >> + phy-mode = "rgmii-id"; >> + ti,syscon-rgmii-delay = <&main_conf 0x4110>; >> + /* Filled in by bootloader */ >> + local-mac-address = [00 00 00 00 00 00]; >> + }; >> + icssg1_emac1: port@1 { >> + reg = <1>; >> + ti,syscon-rgmii-delay = <&main_conf 0x4114>; >> + /* Filled in by bootloader */ >> + local-mac-address = [00 00 00 00 00 00]; >> + status = "disabled"; >> + }; >> + }; >> + }; >> }; >> >> &main_pmx0 { >> @@ -383,6 +452,30 @@ ddr_vtt_pins_default: ddr-vtt-default-pins { >> AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >> >; >> }; >> + >> + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { >> + pinctrl-single,pins = < >> + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ >> + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ >> + >; >> + }; >> + >> + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ >> + pinctrl-single,pins = < >> + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ >> + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ >> + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ >> + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ >> + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ >> + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ >> + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ >> + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ >> + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ >> + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ >> + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ >> + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ >> + >; >> + }; >> }; >> >> &main_uart0 { >> @@ -731,3 +824,15 @@ &main_mcan1 { >> pinctrl-0 = <&main_mcan1_pins_default>; >> phys = <&transceiver2>; >> }; >> + >> +&icssg1_mdio { >> + status = "okay"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&icssg1_mdio1_pins_default>; >> + >> + icssg1_phy1: ethernet-phy@0 { >> + reg = <0xf>; >> + tx-internal-delay-ps = <250>; >> + rx-internal-delay-ps = <2000>; >> + }; >> +}; >> -- >> 2.34.1 >> >
On 18:58-20231207, Anwar, Md Danish wrote: [...] > >> + > >> memory@80000000 { > >> bootph-all; > >> device_type = "memory"; > >> @@ -229,6 +234,70 @@ transceiver2: can-phy1 { > >> max-bitrate = <5000000>; > >> standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; > >> }; > >> + > >> + icssg1_eth: icssg1-eth { > >> + compatible = "ti,am642-icssg-prueth"; > >> + pinctrl-names = "default"; > >> + pinctrl-0 = <&icssg1_rgmii1_pins_default>; > >> + > >> + sram = <&oc_sram>; > >> + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; > >> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", > >> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", > >> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", > >> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", > >> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", > >> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; > > > > Umm... am65x??? is that a typo? I'd rather keep it am64x here and drop > > that sr2 thing. Tomorrow there will be a custom bug on am64 and then we > > will have to respin this again. > > > > No Nishant, this is not a typo. Both AM64x and AM65x use the same ICSSG > firmwares. We only have am65x-sr2-* firmwares and they are used by both > AM64x and AM65x and that is why I have kept the firmware-name here in dt > same as the files that we load on the pru cores. > SoCs are different. The hardware as a result is different as well. In fact, you do have a different compatible to distinguish the two. Some day, there will be an erratum that is different and we will be stuck with abi breakage across distros. So, unless you can explain why this scenario will never occur, I don't buy the argument this will survive long term.
On 12/7/2023 7:13 PM, Nishanth Menon wrote: > On 18:58-20231207, Anwar, Md Danish wrote: > [...] >>>> + >>>> memory@80000000 { >>>> bootph-all; >>>> device_type = "memory"; >>>> @@ -229,6 +234,70 @@ transceiver2: can-phy1 { >>>> max-bitrate = <5000000>; >>>> standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; >>>> }; >>>> + >>>> + icssg1_eth: icssg1-eth { >>>> + compatible = "ti,am642-icssg-prueth"; >>>> + pinctrl-names = "default"; >>>> + pinctrl-0 = <&icssg1_rgmii1_pins_default>; >>>> + >>>> + sram = <&oc_sram>; >>>> + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; >>>> + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", >>>> + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", >>>> + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", >>>> + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", >>>> + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", >>>> + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; >>> >>> Umm... am65x??? is that a typo? I'd rather keep it am64x here and drop >>> that sr2 thing. Tomorrow there will be a custom bug on am64 and then we >>> will have to respin this again. >>> >> >> No Nishant, this is not a typo. Both AM64x and AM65x use the same ICSSG >> firmwares. We only have am65x-sr2-* firmwares and they are used by both >> AM64x and AM65x and that is why I have kept the firmware-name here in dt >> same as the files that we load on the pru cores. >> > > SoCs are different. The hardware as a result is different as well. In > fact, you do have a different compatible to distinguish the two. Some > day, there will be an erratum that is different and we will be stuck > with abi breakage across distros. So, unless you can explain why this > scenario will never occur, I don't buy the argument this will survive > long term. > Agreed, this property was introduced for this purpose only. Today am65x and am64x share the same firmware however in future the firmwares might change and that is why we have this property. Currently this property is not used in driver and firmware name is defined in the driver (with the below structure) which is used for both am64x and am65x. I will rename the firmware names here to am64x-sr2* in v2. In future when we have different firmwares for different SoCs, we can stop using the below structure and use the firmware-name property from dt. static struct icssg_firmwares icssg_emac_firmwares[] = { { .pru = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", .rtu = "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", .txpru = "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", }, { .pru = "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", .rtu = "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", .txpru = "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf", } };
> +&icssg1_mdio { > + status = "okay"; > + pinctrl-names = "default"; > + pinctrl-0 = <&icssg1_mdio1_pins_default>; > + > + icssg1_phy1: ethernet-phy@0 { > + reg = <0xf>; reg = 0xf, so this is ethernet-phy@f. Andrew
On 12/8/2023 3:04 AM, Andrew Lunn wrote: >> +&icssg1_mdio { >> + status = "okay"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&icssg1_mdio1_pins_default>; >> + >> + icssg1_phy1: ethernet-phy@0 { >> + reg = <0xf>; > > reg = 0xf, so this is ethernet-phy@f. > > Andrew Sure Andrew. I'll update this.
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 8c5651d2cf5d..04d1c0602d31 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -34,6 +34,11 @@ aliases { ethernet1 = &cpsw_port2; }; + aliases { + ethernet2 = &icssg1_emac0; + ethernet3 = &icssg1_emac1; + }; + memory@80000000 { bootph-all; device_type = "memory"; @@ -229,6 +234,70 @@ transceiver2: can-phy1 { max-bitrate = <5000000>; standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>; }; + + icssg1_eth: icssg1-eth { + compatible = "ti,am642-icssg-prueth"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_rgmii1_pins_default>; + + sram = <&oc_sram>; + ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>; + firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel = <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt = <&icssg1_mii_g_rt>; + ti,mii-rt = <&icssg1_mii_rt>; + ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + + interrupt-parent = <&icssg1_intc>; + interrupts = <24 0 2>, <25 1 3>; + interrupt-names = "tx_ts0", "tx_ts1"; + + dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */ + <&main_pktdma 0xc201 15>, /* egress slice 0 */ + <&main_pktdma 0xc202 15>, /* egress slice 0 */ + <&main_pktdma 0xc203 15>, /* egress slice 0 */ + <&main_pktdma 0xc204 15>, /* egress slice 1 */ + <&main_pktdma 0xc205 15>, /* egress slice 1 */ + <&main_pktdma 0xc206 15>, /* egress slice 1 */ + <&main_pktdma 0xc207 15>, /* egress slice 1 */ + <&main_pktdma 0x4200 15>, /* ingress slice 0 */ + <&main_pktdma 0x4201 15>; /* ingress slice 1 */ + dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + icssg1_emac0: port@0 { + reg = <0>; + phy-handle = <&icssg1_phy1>; + phy-mode = "rgmii-id"; + ti,syscon-rgmii-delay = <&main_conf 0x4110>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + icssg1_emac1: port@1 { + reg = <1>; + ti,syscon-rgmii-delay = <&main_conf 0x4114>; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + }; + }; }; &main_pmx0 { @@ -383,6 +452,30 @@ ddr_vtt_pins_default: ddr-vtt-default-pins { AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >; }; + + icssg1_mdio1_pins_default: icssg1-mdio1-default-pins { + pinctrl-single,pins = < + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA6) PRG1_MDIO0_MDIO */ + >; + }; + + icssg1_rgmii1_pins_default: icssg1-rgmii1-default-pins{ + pinctrl-single,pins = < + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00e4, PIN_INPUT, 2) /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e8, PIN_INPUT, 2) /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00ec, PIN_INPUT, 2) /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00f0, PIN_INPUT, 2) /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f8, PIN_INPUT, 2) /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f4, PIN_INPUT, 2) /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + >; + }; }; &main_uart0 { @@ -731,3 +824,15 @@ &main_mcan1 { pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; }; + +&icssg1_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&icssg1_mdio1_pins_default>; + + icssg1_phy1: ethernet-phy@0 { + reg = <0xf>; + tx-internal-delay-ps = <250>; + rx-internal-delay-ps = <2000>; + }; +};
ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded. The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2) port is kept disable and ICSSG1 is enabled in single MAC mode by default. Signed-off-by: MD Danish Anwar <danishanwar@ti.com> --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 105 ++++++++++++++++++++++++ 1 file changed, 105 insertions(+)