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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The host wake pin is a standard feature in the PCIe bus specification, so we add this property under PCI dts node to enable the host wake function. Signed-off-by: Sherry Sun Reviewed-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 7507548cdb16..ac824046c594 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -367,6 +367,7 @@ &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + host-wake-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, @@ -545,6 +546,7 @@ pinctrl_pcie1: pcie1grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 >; };