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Fri, 8 Dec 2023 08:47:19 -0800 From: To: , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , , Subject: [PATCH v3 1/2] kvm: arm64: introduce new flag for non-cacheable IO memory Date: Fri, 8 Dec 2023 22:17:08 +0530 Message-ID: <20231208164709.23101-2-ankita@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231208164709.23101-1-ankita@nvidia.com> References: <20231208164709.23101-1-ankita@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E8:EE_|BY5PR12MB4290:EE_ X-MS-Office365-Filtering-Correlation-Id: 7dce19df-0f6c-4579-6aa3-08dbf80d67a0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 81aFlsgEb09PvNF37B5mSazu2R9eDJI3IlZ9AKXDRUX5AGFx+f8EAIkVWgocNhcEVzRM59Esc7hL3dvNfuhXSg8BeZZMwxjS418oTa86IBXlUJIHwNioksDAZgsCdyfizpjo58M+VSZyPHeN1ZjKCH1HRbHMo7GlUDuCb9MxEWKHn46EGY1gfVVTn/jpk1MvFIM4qX5pIWwJ38mDFPUPoej1OTtOzpXdSDVGOvul4N+ZKDsI8i2R9LRxzMv1F5a+DAVvKZoM5dX77CLvEeN52j/fnltq1sG5NNH9I0//8AHA0qut6Wq/6newcNdLWzPX+fTwNcoKIobg4RrYYGSIZdD4mRDfME/0cT9C0bFL4EjUkWpW1OHD9cqLDnvI85f0E/gJjNjlwL91NpSx2YuSHaTTJCiMJxzJo4jrXmBhwtumdgvPM1Ot5PJLxh/DE6iBop1/HP9DQDu7FBkh84afJuTFRrMhs8ummWl6eLaH0jnE/rxq1Z6NjTaDNppGkf6X2CYHIuFKfQhoCE8EezSRw96N0i+FJjq5wmPJE6sqobarnuF8VaIkwjtwuW5+pbk8umIpRVeIl/srCSNgHhIqjmJffXwcYBDhKy1/5IeWZhzO033oVYVEbNW6HAnvnxP731/cUFefqA3AtThLz0lsWGhT8EhXtQ0qOmb72i75W4vp/KOoDMm0YCKjG0YbAJcULsWv2DmnUy+yqXUQlPe+FcfPa7G3RUgabjy6n1W8ilvqwRvCdG4RWO3fg0O6QUoeOy8qnqMg5BUq8LS24EWPJIF9VF8YFWGFZ230JER8TbpvjDpalYJF5J1baRZt80+V X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(376002)(346002)(230922051799003)(186009)(451199024)(1800799012)(64100799003)(82310400011)(36840700001)(46966006)(40470700004)(47076005)(40460700003)(4326008)(110136005)(41300700001)(70586007)(478600001)(54906003)(316002)(36756003)(86362001)(8936002)(8676002)(70206006)(19627235002)(2616005)(921008)(2906002)(2876002)(5660300002)(7416002)(7636003)(356005)(1076003)(7696005)(36860700001)(82740400003)(83380400001)(6666004)(426003)(336012)(26005)(40480700001)(2101003)(83996005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Dec 2023 16:47:45.8480 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7dce19df-0f6c-4579-6aa3-08dbf80d67a0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4290 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231208_084753_740790_9331DE14 X-CRM114-Status: GOOD ( 12.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Ankit Agrawal For various reasons described in the cover letter, and primarily to allow VM get IO memory with NORMALNC properties, it is desired to relax the KVM stage 2 device memory attributes from DEVICE_nGnRE to NormalNC. So set S2 PTE for IO memory as NORMAL_NC. A Normal-NC flag is not present today. So add a new kvm_pgtable_prot (KVM_PGTABLE_PROT_NORMAL_NC) flag for it, along with its corresponding PTE value 0x5 (0b101) determined from [1]. Lastly, adapt the stage2 PTE property setter function (stage2_set_prot_attr) to handle the NormalNC attribute. [1] section D8.5.5 of DDI0487J_a_a-profile_architecture_reference_manual.pdf Signed-off-by: Ankit Agrawal Suggested-by: Jason Gunthorpe Acked-by: Catalin Marinas Tested-by: Ankit Agrawal Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/kvm_pgtable.h | 2 ++ arch/arm64/include/asm/memory.h | 2 ++ arch/arm64/kvm/hyp/pgtable.c | 11 +++++++++-- 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h index cfdf40f734b1..19278dfe7978 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -197,6 +197,7 @@ enum kvm_pgtable_stage2_flags { * @KVM_PGTABLE_PROT_W: Write permission. * @KVM_PGTABLE_PROT_R: Read permission. * @KVM_PGTABLE_PROT_DEVICE: Device attributes. + * @KVM_PGTABLE_PROT_NORMAL_NC: Normal noncacheable attributes. * @KVM_PGTABLE_PROT_SW0: Software bit 0. * @KVM_PGTABLE_PROT_SW1: Software bit 1. * @KVM_PGTABLE_PROT_SW2: Software bit 2. @@ -208,6 +209,7 @@ enum kvm_pgtable_prot { KVM_PGTABLE_PROT_R = BIT(2), KVM_PGTABLE_PROT_DEVICE = BIT(3), + KVM_PGTABLE_PROT_NORMAL_NC = BIT(4), KVM_PGTABLE_PROT_SW0 = BIT(55), KVM_PGTABLE_PROT_SW1 = BIT(56), diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h index fde4186cc387..c247e5f29d5a 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -147,6 +147,7 @@ * Memory types for Stage-2 translation */ #define MT_S2_NORMAL 0xf +#define MT_S2_NORMAL_NC 0x5 #define MT_S2_DEVICE_nGnRE 0x1 /* @@ -154,6 +155,7 @@ * Stage-2 enforces Normal-WB and Device-nGnRE */ #define MT_S2_FWB_NORMAL 6 +#define MT_S2_FWB_NORMAL_NC 5 #define MT_S2_FWB_DEVICE_nGnRE 1 #ifdef CONFIG_ARM64_4K_PAGES diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index c651df904fe3..d4835d553c61 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -718,10 +718,17 @@ static int stage2_set_prot_attr(struct kvm_pgtable *pgt, enum kvm_pgtable_prot p kvm_pte_t *ptep) { bool device = prot & KVM_PGTABLE_PROT_DEVICE; - kvm_pte_t attr = device ? KVM_S2_MEMATTR(pgt, DEVICE_nGnRE) : - KVM_S2_MEMATTR(pgt, NORMAL); + bool normal_nc = prot & KVM_PGTABLE_PROT_NORMAL_NC; + kvm_pte_t attr; u32 sh = KVM_PTE_LEAF_ATTR_LO_S2_SH_IS; + if (device) + attr = KVM_S2_MEMATTR(pgt, DEVICE_nGnRE); + else if (normal_nc) + attr = KVM_S2_MEMATTR(pgt, NORMAL_NC); + else + attr = KVM_S2_MEMATTR(pgt, NORMAL); + if (!(prot & KVM_PGTABLE_PROT_X)) attr |= KVM_PTE_LEAF_ATTR_HI_S2_XN; else if (device)