From patchwork Tue Dec 12 11:16:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 13489003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0EF49C4332F for ; Tue, 12 Dec 2023 11:17:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mcfwgOA7tDzTHzpZtY2CtlC0J8olXfz+Z5iMOoggBRA=; b=0CCyBSlRAorJaU KQ6bkMqkrcuvv3KxP/jY2tjacQ9WTAn557DkXTa+ir6KxBslKtFAiH63lwP7wBEXpkBccEJege+5G 7w+twHsjEbdPsrnBiuRafRTtHVTtiXrenX45T0AD9pDCkY882JapLTrcgebpaVphEP0BcufHsu+Ba 1hNEHWw6T+P+R1Vb/tkoDIWBkistPj7uS/JxC8Vy3RlTOcXlpmHW0aqNhHhcf+Fqu58eKlHt9KBXh r6/CO89KFAg/uqlB9wp3cyRIvEq3GvSXcEWo48nI4VSY/ue2OQzfW3ONHTorvRtc6QMHGKfRfKhER EaDoAK4TMdOa4BWaqkWg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rD0ky-00BS5T-1D; Tue, 12 Dec 2023 11:16:56 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rD0kt-00BS01-30 for linux-arm-kernel@lists.infradead.org; Tue, 12 Dec 2023 11:16:53 +0000 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3BCBGjUY054355; Tue, 12 Dec 2023 05:16:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1702379805; bh=YRXnu3KKk5rVSp9bSrZSmJTFJNBJZ6VGFKc3R8e51ys=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=s2nnMABpgNG4C6tLTVQms12kXJClJpKCCmZ/bnSrMCQuGKrZuGauSK47hHW9DkXV8 DWxPAFUhk9Z3auCK6eKU9sJM9YQorEPo5FHLALv+8OJ1Zw2qnHnExFcmFw5NiTfPPO pbiWJU+FtytAjrxMR7PJswA7Fma+1mWeuLEW6mR0= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3BCBGjXv019489 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 12 Dec 2023 05:16:45 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 12 Dec 2023 05:16:45 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 12 Dec 2023 05:16:45 -0600 Received: from uda0132425.dhcp.ti.com (uda0132425.dhcp.ti.com [172.24.227.94]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3BCBGd8X094897; Tue, 12 Dec 2023 05:16:43 -0600 From: Vignesh Raghavendra To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , Subject: [PATCH 1/3] arm64: dts: ti: k3-am65: Add additional regs for DMA components Date: Tue, 12 Dec 2023 16:46:32 +0530 Message-ID: <20231212111634.3515175-2-vigneshr@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231212111634.3515175-1-vigneshr@ti.com> References: <20231212111634.3515175-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231212_031652_056256_540F9320 X-CRM114-Status: GOOD ( 10.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Manorit Chawdhry Add additional reg properties for UDMA and RingAcc nodes which are mostly used by bootloader components before Device Manager firmware services are available, in order to setup DMA transfers. Signed-off-by: Manorit Chawdhry Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++++-- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 5ebb87f467de..2033a8ec89d6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -790,8 +790,12 @@ main_udmap: dma-controller@31150000 { compatible = "ti,am654-navss-main-udmap"; reg = <0x0 0x31150000 0x0 0x100>, <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; + <0x0 0x35000000 0x0 0x100000>, + <0x0 0x30b00000 0x0 0x20000>, + <0x0 0x30c00000 0x0 0x8000>, + <0x0 0x30d00000 0x0 0x4000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index edd5cfbec40e..ecd7356f3315 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -214,8 +214,12 @@ mcu_udmap: dma-controller@285c0000 { compatible = "ti,am654-navss-mcu-udmap"; reg = <0x0 0x285c0000 0x0 0x100>, <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; - reg-names = "gcfg", "rchanrt", "tchanrt"; + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchanrt", "tchanrt", + "tchan", "rchan", "rflow"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>;