From patchwork Wed Dec 20 14:57:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 13500204 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28309C3DA6E for ; Wed, 20 Dec 2023 15:00:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iM3cD9a2vamSun9SEZIKpNGToNmIIa1/Ib7txH5xAL8=; b=Dj7d04SLsWC7+M 7ApV7HYELvuf/lEvvQKFZRLpz4hworfNT/t9x6yXPHbFlWxEx2lE1uVtTl0xhiWv2u0CxMfFMOa7G I6xmQ8ZfgaPfSEk0NDA2cLAcGZgsqyLqZfFfk9rYXOKGRQg6+60sEVRz2AtiayofdwsRu5Pb5ONXD QPJk19e55CF7dLPXZwtDUMXuTjw4pbyoMYt/bQLBEyNw2acsKSEAy3/bkwj9UcJF2+Rjb46nG/9zC CdoAChg5NgOPgXDEU3U/qnUwtcilYqS7lF3nbRh7IbE2HPg8zD+BJP0DVZVZ7TH2rRWpAlrlD4J7/ jDx0nTHogxpYk2l4YpdQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rFy2y-0009lZ-1d; Wed, 20 Dec 2023 14:59:44 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rFy2m-0009ep-2y for linux-arm-kernel@lists.infradead.org; Wed, 20 Dec 2023 14:59:35 +0000 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3BKAKkOd026644; Wed, 20 Dec 2023 15:59:27 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=27s5gqZ8CpISwz9sEJ9KmbSXmWANFBZJ5F5PfijotM8=; b=jm kLz3peXIJp5C6TZiOexzA+OZKxXTWuRGD8rCxAQxXFjuptl+CrFh4AWQ+i0RvL5f LtLMEDhYcILupjq9+azz3zwCBpTM0NxT2GjIsw0FxWnfYj70X4OmLTSSU/AG/ouA QiMLglJGLQtINcCxhFQECmelzV4AKgRNsGZ5sm4+mGHP3MlFT1F5esfAxwYC8bCQ W8vdReyTzSRT+fo6BC2vDcC4pOnwQ0gQmIkdS5qZYzCQgHNWV1dtRf5dMgdj8O01 fRpv6Sc0PUIzXNRhMmaJrZ9c0X2F8FT5DwwUhXv5waS+CqCwHpVFzLa+19k5NUHr ni/7Mjhr6ObDm7DEpd+g== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3v11w91wfe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Dec 2023 15:59:08 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0DDD3100059; Wed, 20 Dec 2023 15:59:08 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 00A9421B51D; Wed, 20 Dec 2023 15:59:08 +0100 (CET) Received: from localhost (10.201.20.59) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 20 Dec 2023 15:59:07 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v3 05/10] counter: stm32-timer-cnt: add counter prescaler extension Date: Wed, 20 Dec 2023 15:57:21 +0100 Message-ID: <20231220145726.640627-6-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> References: <20231220145726.640627-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.59] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-20_08,2023-12-20_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231220_065933_233718_A8F54C7F X-CRM114-Status: GOOD ( 11.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There's a prescaler in between the selected input signal used for counting (CK_PSC), and the counter input (CK_CNT). So add the "prescaler" extension to the counter. Signed-off-by: Fabrice Gasnier Reviewed-by: William Breathitt Gray --- Changes in v3: - New patch split from "counter: stm32-timer-cnt: introduce clock signal" --- drivers/counter/stm32-timer-cnt.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 21a9c20c4281..bf2726dd7f12 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -220,11 +220,40 @@ static int stm32_count_enable_write(struct counter_device *counter, return 0; } +static int stm32_count_prescaler_read(struct counter_device *counter, + struct counter_count *count, u64 *prescaler) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 psc; + + regmap_read(priv->regmap, TIM_PSC, &psc); + + *prescaler = psc + 1; + + return 0; +} + +static int stm32_count_prescaler_write(struct counter_device *counter, + struct counter_count *count, u64 prescaler) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 psc; + + if (!prescaler || prescaler > MAX_TIM_PSC + 1) + return -ERANGE; + + psc = prescaler - 1; + + return regmap_write(priv->regmap, TIM_PSC, psc); +} + static struct counter_comp stm32_count_ext[] = { COUNTER_COMP_DIRECTION(stm32_count_direction_read), COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), COUNTER_COMP_CEILING(stm32_count_ceiling_read, stm32_count_ceiling_write), + COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, + stm32_count_prescaler_write), }; static const enum counter_synapse_action stm32_clock_synapse_actions[] = {