From patchwork Thu Jan 4 11:19:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neha Malcom Francis X-Patchwork-Id: 13511021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 08417C47074 for ; Thu, 4 Jan 2024 11:20:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=5qfhG7xlP/8PnOnw+ffQVWTKjEScVa7QfZ3evsXHpAw=; b=tj9j6n3CC+Vb9H 0/OQuO3o854aGO9O+zWBpJr47Td6eUVL3EpEdz+y4Ny5dJ/1hz7w8IXzXib6NyPmuPMrcRMUq1nzh dkXAedrM4oR3oeQD8rtKwODHbDRDf6UJxhQd/K6KdYXJtn1g3bn/ec5rbNEuaHu9dZdZl98V012jb HwfWgZRmWzxRQ++FmJqpgByeyV/CAITiWuDDgkjNroCGKXosNPpGrXgyYZnfivpZBleId0SOyLHuD 3lGGkcGrUKyRaTokf9bob/nq7VdGqrFFcY1VPfA0oMFRMsqyAYYux5voU+u331nJBHfKkQiLQ58Ly PR+A/HRqJ+Ks3lJHnMQA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rLLlE-00DgWr-0C; Thu, 04 Jan 2024 11:19:40 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rLLlA-00DgVJ-1K for linux-arm-kernel@lists.infradead.org; Thu, 04 Jan 2024 11:19:38 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 404BJQfJ124161; Thu, 4 Jan 2024 05:19:26 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1704367166; bh=gEI1DUvl7fwMGnh7BriCsJR03yIbeB6SbxVvjDA9xHg=; h=From:To:CC:Subject:Date; b=BCIiI5a9PeRs0T+tkg67xaVWYXo85oT6EKzgsRzyOcJr+aOblB0QhLpEyANNkOLRV Ra0gpt21YLCm/FMycxD/NDXIKKrIJSaGhDriliaDketlmqnGL5z7AiYdaW5RKcHhLf 62VDJ30ArdkfeUuVCP6fcyWcpm3ImUNbQa+y8cac= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 404BJQtm117077 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 4 Jan 2024 05:19:26 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 4 Jan 2024 05:19:26 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 4 Jan 2024 05:19:26 -0600 Received: from a0497641-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (a0497641-hp-z2-tower-g9-workstation-desktop-pc.dhcp.ti.com [172.24.227.36]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 404BJMmS111184; Thu, 4 Jan 2024 05:19:23 -0600 From: Neha Malcom Francis To: , , , CC: , , , , , , Subject: [PATCH v2] arm64: dts: ti: k3-j721e: Add support for DFS in J721E A72 Date: Thu, 4 Jan 2024 16:49:22 +0530 Message-ID: <20240104111922.832040-1-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240104_031936_613527_12634684 X-CRM114-Status: GOOD ( 12.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add 2G, 1G, 500M and 250M as the supported frequencies for A72. This enables support for Dynamic Frequency Scaling (DFS). Note that Dynamic Voltage and Frequency Scaling (DVFS) is not supported on J7 devices. J721E SoC has three different speed grade devices (see [1], 7.5 Operating Performance Points) which as of today are indiscernible in software, users of a different speed grade device must manually change the DTS to ensure their maximum speed frequency is supported. To obtain clock-latency-ns, the maximum time was found to switch from/to any frequency for a CPU and this value was rounded off and set. [1] https://www.ti.com/lit/gpn/tda4vm Signed-off-by: Neha Malcom Francis --- Test and boot logs: https://gist.github.com/nehamalcom/33608837ab5ad3332ff11a7fa7a602e2 Changes since v1: https://lore.kernel.org/all/20231214075637.176586-1-n-francis@ti.com/ - removed OPPs 1.5G and 750M as they introduced boot regression in J721E-SK - Nishanth - indicated DVFS not supported in commit message - moved critical data sheet info from below tear line to commit message - added opp-shared property - added clock-latency-ns property arch/arm64/boot/dts/ti/k3-j721e.dtsi | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index a200810df54a..5de6c70bd989 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -48,6 +48,9 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 202 2>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; }; cpu1: cpu@1 { @@ -62,6 +65,34 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&L2_0>; + clocks = <&k3_clks 203 0>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp6-2000000000 { + opp-hz = /bits/ 64 <2000000000>; + clock-latency-ns = <300000>; + }; + + opp4-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + clock-latency-ns = <300000>; + }; + + opp2-500000000 { + opp-hz = /bits/ 64 <500000000>; + clock-latency-ns = <300000>; + }; + + opp1-250000000 { + opp-hz = /bits/ 64 <250000000>; + clock-latency-ns = <300000>; }; };