From patchwork Wed Jan 17 16:14:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Diogo Ivo X-Patchwork-Id: 13522003 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D43E7C47DA9 for ; Wed, 17 Jan 2024 16:16:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CtaIphNUvNRq5MZf6RtxcdNcESaxsdGcendoXG9lPQA=; b=ozYE84nSi7EWCB bxwp47YWFEsG+SPUevxccjxkynn0U+DpSoosu58pYS6EcgiXjfhSrQaVOuFXE+q4cztlD/0Xh4RGl AvJWj35h4pY21jFbiA25pTk9jAFfMIx8Snq2KZHCJWJG06FS5+Yasqxu1IlnXLpKNWiJLqZgfRPEA r3RF0eADHKbwPdsEmX3NIXZMRlzN0Fkf+6zVLVbwWwlz0GUSwNttmc9RczjEREoJmbL9Gsn77lDFR /B4MkYZW6eF1haPPnrsBmjBwlhrvSUpXMqwi5xu1coQ60hCKkSW0hEVlB2u4IgKjoFuApKNHlusXE 0Ih8CDnoAA3gvK4UU/+Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rQ8aX-0001ca-1t; Wed, 17 Jan 2024 16:16:26 +0000 Received: from mta-64-227.siemens.flowmailer.net ([185.136.64.227]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rQ8aS-0001Yn-2d for linux-arm-kernel@lists.infradead.org; Wed, 17 Jan 2024 16:16:23 +0000 Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 20240117161614e34ceea4fc280bab09 for ; Wed, 17 Jan 2024 17:16:14 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=diogo.ivo@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=V3s9GK0OAb3raYOYAIncj1wCgS57eQxkjBGUikPp6W0=; b=RB4sQcLSvKLe8EBRQL3S8i2ZZjm5pTE+r05xsWSijLbO0i4/k8v+bl4TkMe6T67cBAkQ12 u9f9/jTJdrW5nPd0YwJ7LTl1U04OYJ0JlUa6mOkNaUgDgPFoNN1diKnupv9HOWtu0Tji3yTl ONJfs9/tv/BSNEqbFbXMU+/BCgzwI=; From: Diogo Ivo To: danishanwar@ti.com, rogerq@kernel.org, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org Cc: Diogo Ivo , Jan Kiszka Subject: [PATCH v2 1/8] dt-bindings: net: Add support for AM65x SR1.0 in ICSSG Date: Wed, 17 Jan 2024 16:14:55 +0000 Message-ID: <20240117161602.153233-2-diogo.ivo@siemens.com> In-Reply-To: <20240117161602.153233-1-diogo.ivo@siemens.com> References: <20240117161602.153233-1-diogo.ivo@siemens.com> MIME-Version: 1.0 X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-1320519:519-21489:flowmailer X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240117_081621_629488_5A2CD056 X-CRM114-Status: UNSURE ( 9.16 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Silicon Revision 1.0 of the AM65x came with a slightly different ICSSG support: Only 2 PRUs per slice are available and instead 2 additional DMA channels are used for management purposes. We have no restrictions on specified PRUs, but the DMA channels need to be adjusted. Co-developed-by: Jan Kiszka Signed-off-by: Jan Kiszka Signed-off-by: Diogo Ivo --- Changes in v2: - Removed explicit reference to SR2.0 - Moved sr1 to the SoC name - Expand dma-names list and adjust min/maxItems depending on SR1.0/2.0 .../bindings/net/ti,icssg-prueth.yaml | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml index 229c8f32019f..59a3292191d9 100644 --- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml +++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml @@ -19,8 +19,9 @@ allOf: properties: compatible: enum: - - ti,am642-icssg-prueth # for AM64x SoC family - - ti,am654-icssg-prueth # for AM65x SoC family + - ti,am642-icssg-prueth # for AM64x SoC family + - ti,am654-icssg-prueth # for AM65x SoC family + - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0 sram: $ref: /schemas/types.yaml#/definitions/phandle @@ -28,8 +29,7 @@ properties: phandle to MSMC SRAM node dmas: - maxItems: 10 - + minItems: 10 dma-names: items: - const: tx0-0 @@ -42,6 +42,8 @@ properties: - const: tx1-3 - const: rx0 - const: rx1 + - const: rxmgm0 + - const: rxmgm1 ti,mii-g-rt: $ref: /schemas/types.yaml#/definitions/phandle @@ -132,6 +134,25 @@ required: - interrupts - interrupt-names +allOf: + - if: + properties: + compatible: + contains: + const: ti,am654-sr1-icssg-prueth + then: + properties: + dmas: + minItems: 12 + dma-names: + minItems: 12 + else: + properties: + dmas: + maxItems: 10 + dma-names: + maxItems: 10 + unevaluatedProperties: false examples: