| Message ID | 20240125173534.1659317-1-ryan.roberts@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] arm64/mm: Make set_ptes() robust when OAs cross 48-bit boundary | expand |
On Thu, Jan 25, 2024 at 05:35:34PM +0000, Ryan Roberts wrote: > Since the high bits [51:48] of an OA are not stored contiguously in the > PTE, there is a theoretical bug in set_ptes(), which just adds PAGE_SIZE > to the pte to get the pte with the next pfn. This works until the pfn > crosses the 48-bit boundary, at which point we overflow into the upper > attributes. > > Of course one could argue (and Matthew Wilcox has :) that we will never > see a folio cross this boundary because we only allow naturally aligned > power-of-2 allocation, so this would require a half-petabyte folio. So > its only a theoretical bug. But its better that the code is robust > regardless. > > I've implemented pte_next_pfn() as part of the fix, which is an opt-in > core-mm interface. So that is now available to the core-mm, which will > be needed shortly to support forthcoming fork()-batching optimizations. > > Fixes: 4a169d61c2ed ("arm64: implement the new page table range API") > Closes: https://lore.kernel.org/linux-mm/fdaeb9a5-d890-499a-92c8-d171df43ad01@arm.com/ > Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> > --- > > Hi All, > > This applies on top of v6.8-rc1. It's a dependency for David's fork-batch > work, so once Catalin has acked it, it will go through mm-unstable attached to > David's series. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
On 25/01/2024 17:43, Catalin Marinas wrote: > On Thu, Jan 25, 2024 at 05:35:34PM +0000, Ryan Roberts wrote: >> Since the high bits [51:48] of an OA are not stored contiguously in the >> PTE, there is a theoretical bug in set_ptes(), which just adds PAGE_SIZE >> to the pte to get the pte with the next pfn. This works until the pfn >> crosses the 48-bit boundary, at which point we overflow into the upper >> attributes. >> >> Of course one could argue (and Matthew Wilcox has :) that we will never >> see a folio cross this boundary because we only allow naturally aligned >> power-of-2 allocation, so this would require a half-petabyte folio. So >> its only a theoretical bug. But its better that the code is robust >> regardless. >> >> I've implemented pte_next_pfn() as part of the fix, which is an opt-in >> core-mm interface. So that is now available to the core-mm, which will >> be needed shortly to support forthcoming fork()-batching optimizations. >> >> Fixes: 4a169d61c2ed ("arm64: implement the new page table range API") >> Closes: https://lore.kernel.org/linux-mm/fdaeb9a5-d890-499a-92c8-d171df43ad01@arm.com/ >> Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> >> --- >> >> Hi All, >> >> This applies on top of v6.8-rc1. It's a dependency for David's fork-batch >> work, so once Catalin has acked it, it will go through mm-unstable attached to >> David's series. > > Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Thanks!
On 25.01.24 18:35, Ryan Roberts wrote: > Since the high bits [51:48] of an OA are not stored contiguously in the > PTE, there is a theoretical bug in set_ptes(), which just adds PAGE_SIZE > to the pte to get the pte with the next pfn. This works until the pfn > crosses the 48-bit boundary, at which point we overflow into the upper > attributes. > > Of course one could argue (and Matthew Wilcox has :) that we will never > see a folio cross this boundary because we only allow naturally aligned > power-of-2 allocation, so this would require a half-petabyte folio. So > its only a theoretical bug. But its better that the code is robust > regardless. > > I've implemented pte_next_pfn() as part of the fix, which is an opt-in > core-mm interface. So that is now available to the core-mm, which will > be needed shortly to support forthcoming fork()-batching optimizations. > > Fixes: 4a169d61c2ed ("arm64: implement the new page table range API") > Closes: https://lore.kernel.org/linux-mm/fdaeb9a5-d890-499a-92c8-d171df43ad01@arm.com/ > Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> > --- > > Hi All, > > This applies on top of v6.8-rc1. It's a dependency for David's fork-batch > work, so once Catalin has acked it, it will go through mm-unstable attached to > David's series. > Reviewed-by: David Hildenbrand <david@redhat.com> I'll include that in my fork() batching series v2 that I'll probably send out tomorrow.
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 79ce70fbb751..52d0b0a763f1 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -341,6 +341,22 @@ static inline void __sync_cache_and_tags(pte_t pte, unsigned int nr_pages) mte_sync_tags(pte, nr_pages); } +/* + * Select all bits except the pfn + */ +static inline pgprot_t pte_pgprot(pte_t pte) +{ + unsigned long pfn = pte_pfn(pte); + + return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); +} + +#define pte_next_pfn pte_next_pfn +static inline pte_t pte_next_pfn(pte_t pte) +{ + return pfn_pte(pte_pfn(pte) + 1, pte_pgprot(pte)); +} + static inline void set_ptes(struct mm_struct *mm, unsigned long __always_unused addr, pte_t *ptep, pte_t pte, unsigned int nr) @@ -354,7 +370,7 @@ static inline void set_ptes(struct mm_struct *mm, if (--nr == 0) break; ptep++; - pte_val(pte) += PAGE_SIZE; + pte = pte_next_pfn(pte); } } #define set_ptes set_ptes @@ -433,16 +449,6 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte) return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE)); } -/* - * Select all bits except the pfn - */ -static inline pgprot_t pte_pgprot(pte_t pte) -{ - unsigned long pfn = pte_pfn(pte); - - return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte)); -} - #ifdef CONFIG_NUMA_BALANCING /* * See the comment in include/linux/pgtable.h
Since the high bits [51:48] of an OA are not stored contiguously in the PTE, there is a theoretical bug in set_ptes(), which just adds PAGE_SIZE to the pte to get the pte with the next pfn. This works until the pfn crosses the 48-bit boundary, at which point we overflow into the upper attributes. Of course one could argue (and Matthew Wilcox has :) that we will never see a folio cross this boundary because we only allow naturally aligned power-of-2 allocation, so this would require a half-petabyte folio. So its only a theoretical bug. But its better that the code is robust regardless. I've implemented pte_next_pfn() as part of the fix, which is an opt-in core-mm interface. So that is now available to the core-mm, which will be needed shortly to support forthcoming fork()-batching optimizations. Fixes: 4a169d61c2ed ("arm64: implement the new page table range API") Closes: https://lore.kernel.org/linux-mm/fdaeb9a5-d890-499a-92c8-d171df43ad01@arm.com/ Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> --- Hi All, This applies on top of v6.8-rc1. It's a dependency for David's fork-batch work, so once Catalin has acked it, it will go through mm-unstable attached to David's series. changes since v1: - Removed pte_pgprot() optimization to aid integration with Ard's LPA2 series, per Catalin's request. Thanks, Ryan arch/arm64/include/asm/pgtable.h | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) -- 2.25.1