From patchwork Thu Feb 1 13:07:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 13541086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C53C0C4828F for ; Thu, 1 Feb 2024 13:38:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:CC:To:In-Reply-To:References:Message-ID :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GN/+RIGDUsfQRv+4lusyL+4q7w7AcxDr3Pmnaq4DtD8=; b=tr1Od3RXO+lKjf tQgsiOlIxbdOFaHB3RnaroWjEcGBygr/o3Qx/+vb1PbgkHPAoMl64399RO7RQxEwJg12bYTn9RSgC Qx69uL+J5vuPqzNob9p+H4KpsXcONqZukB+UupCEHlYuwnCaPW7ebg1m2iTfdZ9BwIxBtEShDJQtT QWTTlmDoWbtY3JG2bSBaEbEbUdWHQu7ozRoTxfb3WcTdqrr3zD6OAm6lj+YdBJoIkDqCYbK/RdlOW FdD48Pd0C8FInFCESilVAH6HGk0weNUAIQ4iuzVS4hXUvSMAeS6Kb6Qq3D94CNZOB6P29Oz1KiPs8 0Ap7lNcARBdydp4NcPSw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVXGb-0000000879L-0c3r; Thu, 01 Feb 2024 13:38:09 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rVWme-00000007uMG-3wjK for linux-arm-kernel@lists.infradead.org; Thu, 01 Feb 2024 13:07:16 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 411D7AnU111374; Thu, 1 Feb 2024 07:07:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1706792830; bh=jokkh7mm/vApO8cJ2IgO8lvQ0Jxmj4g+5elU4Bg1bf0=; h=From:Date:Subject:References:In-Reply-To:To:CC; b=r282Ms255/nIRnj88+3M/JfpW/Pv/lJ3UZjPropVIF/Uc//UlXNURvkgy7E8wH4A3 xsaRKrvSyp04oXH9VTA8+xoyHofqCdizaGv2emVCDtVY+yF75/WEszViaGr0sSZQTM VC6U/hagsRrhLB7wc2RQ0JL34rQyIaqlvQovafvQ= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 411D7ALf121103 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Feb 2024 07:07:10 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Feb 2024 07:07:09 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Feb 2024 07:07:09 -0600 Received: from localhost (jluthra.dhcp.ti.com [172.24.227.217]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 411D78Sp012827; Thu, 1 Feb 2024 07:07:09 -0600 From: Jai Luthra Date: Thu, 1 Feb 2024 18:37:00 +0530 Subject: [PATCH 1/4] arm64: dts: ti: k3-am62p: Fix memory ranges for DMSS MIME-Version: 1.0 Message-ID: <20240201-am62p_csi-v1-1-c83bb9eaeb49@ti.com> References: <20240201-am62p_csi-v1-0-c83bb9eaeb49@ti.com> In-Reply-To: <20240201-am62p_csi-v1-0-c83bb9eaeb49@ti.com> To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Bryan Brattlof , Dhruva Gole CC: , , , Vaishnav Achath , Devarsh Thakkar , Aradhya Bhatia , Jai Luthra X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1288; i=j-luthra@ti.com; h=from:subject:message-id; bh=1CMmX3jd2pLUCqu+EFJBJO2nN+pqTZAQeqrdSBzj0jg=; b=owEBbQKS/ZANAwAIAUPekfkkmnFFAcsmYgBlu5d31SanWbJPLAw6IkCBDYpbCnLupNV7p50ky npr9EsviW6JAjMEAAEIAB0WIQRN4NgY5dV16NRar8VD3pH5JJpxRQUCZbuXdwAKCRBD3pH5JJpx RWW3D/9brVgwvqumRvQwKdedaNFFpsPh1+tqTV2yhjv649jdQpJ0kOK8nN7BR2AVhFDdAwuZ7Ox HXASrP0FlJ5hmpPskOhdrs3ps82JerRhKy0r4t8uFaHsO4aOy1rB6s7rdI6QUJahxCkSSNX5Dii XQ0HiiQzcVmOwtDaDj1JS1SpGmLuLIr/sVEm/MLQzlZmOWEsWSMFXV3GqDt7CYtCqeyd6U/xw+2 xZyX4vu9fkQsGVP+LeakRTdgpJMLPsEvkiH3AB90UL32zhWPd4TzKFq1NlRuNg4xlsZBdZhxATX fhMoooWjwuctgyLwrR9g7VvperRffDlCOiMfYiwTFqd485Dhi/X0+3KN+4bwWbLFp/ueWkErRsp o2mSdNKSpNNUBW+w0afHmt70md8BweShcStAu5GEydfn7RVkPryIQkk3SbQi7IXVVRBfuL6Z0uQ 1YKBgVs/GqAI0ckp8qd9z8NcUIu5WBIM0rqoNj91a2rChPSe0ef5qlIewuYuv6phhM/YLWVNkwn DIzYPMW+lM4GGEXIp3LyB0KEVKuElGGa9Kf6I0GQ1d3yLQ26cfXa+4Wg3N+Qnj7ycycoglCIJSo zW2ey7ZIbyFlZiVdvnR8krRa8rpCZvnNe+9yLzUi/qz1rXmQPxGMYKnvXmeCAe7b33a4ljsZGwL YsIB3+/rTqcW7PQ== X-Developer-Key: i=j-luthra@ti.com; a=openpgp; fpr=4DE0D818E5D575E8D45AAFC543DE91F9249A7145 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240201_050713_135862_16CBFD7A X-CRM114-Status: GOOD ( 10.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The INTR module for DMASS1 (CSI specific DMASS) is outside the currently available ranges, as it starts at 0x4e400000. So fix the ranges property to enable programming the interrupts correctly. Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs") Signed-off-by: Jai Luthra Reviewed-by: Vaishnav Achath --- arch/arm64/boot/dts/ti/k3-am62p.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index 84ffe7b9dcaf..4f22b5d9fb9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -71,7 +71,7 @@ cbass_main: bus@f0000 { <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ - <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */