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Mon, 05 Feb 2024 09:20:26 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCU1elTh9SN9v38NWSf1rePgCvyzfn4m3+8JVqdjjh6w7OZ6L0CGN1+JXZrPiCubQSIt1FC+FebLlf7otoIHL3l3/COk0aMmn1hDP2lr1uBiyARxiTxr8t6gkk4e9zJFIZdJhE6Ydm9OGYHAIm3Fi8Rwhi/on81QuDIyh5LIdF7lVEPd0qsY/ePDkDp2mBfn20JIQ1ojwUSMeUoBZqT7u5v8MTkeH0Gd38K8oMMcXiP3UJb9OcZIqME/TRBuKLSjIV8YZ2NY/2rVcG8sVE+Urt0w492I16BJWdu7rkYtgSBzb8X+T+uJnk1FbCfH4xw3f+qliQz6OZPdr/lutNmekGYOEOhEPavZnNmBoKrf8IVRB8Npvr6dqrAAcWij4EGdFoD9R7jY2irgrY8q1+Y/kGa0WsgmsQRBxll+ctUw9/Gb2jPPLOR1dBEUEAB5i6M0YFtL/g3V Received: from localhost.localdomain ([113.30.217.222]) by smtp.gmail.com with ESMTPSA id iy15-20020a170903130f00b001d8f3c7fb96sm107518plb.166.2024.02.05.09.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Feb 2024 09:20:25 -0800 (PST) From: Anand Moon To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: Anand Moon , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCHv1 2/5] arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC Date: Mon, 5 Feb 2024 22:49:20 +0530 Message-ID: <20240205171930.968-3-linux.amoon@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240205171930.968-1-linux.amoon@gmail.com> References: <20240205171930.968-1-linux.amoon@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240205_092027_600267_B73D17EA X-CRM114-Status: GOOD ( 10.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org As per S905X3 datasheet add missing cache information to the Amlogic SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache. - Each Cortex-A55 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 512KB Unified L3 cache. To improve system performance. Signed-off-by: Anand Moon --- Datasheet [0] https://dn.odroid.com/S905X3/ODROID-C4/Docs/S905X3_Public_Datasheet_Hardkernel.pdf [1] https://en.wikipedia.org/wiki/ARM_Cortex-A55 --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 39 ++++++++++++++++++---- 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 643f94d9d08e..403443e782e4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -55,7 +55,13 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l3>; #cooling-cells = <2>; }; @@ -64,7 +70,13 @@ cpu1: cpu@1 { compatible = "arm,cortex-a55"; reg = <0x0 0x1>; enable-method = "psci"; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l3>; #cooling-cells = <2>; }; @@ -73,7 +85,13 @@ cpu2: cpu@2 { compatible = "arm,cortex-a55"; reg = <0x0 0x2>; enable-method = "psci"; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l3>; #cooling-cells = <2>; }; @@ -82,14 +100,23 @@ cpu3: cpu@3 { compatible = "arm,cortex-a55"; reg = <0x0 0x3>; enable-method = "psci"; - next-level-cache = <&l2>; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; + next-level-cache = <&l3>; #cooling-cells = <2>; }; - l2: l2-cache0 { + l3: l3-cache0 { compatible = "cache"; - cache-level = <2>; + cache-level = <3>; cache-unified; + cache-size = <0x7d000>; /* L2. 512 KB */ + cache-line-size = <64>; + cache-sets = <512>; }; };