| Message ID | 20240205194706.3605309-2-b-brnich@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Support for Wave5 on TI Devices | expand |
Hi Brandon On 06/02/24 01:17, Brandon Brnich wrote: > This patch adds support for the Wave521cl on the J784S4-evm. > > Signed-off-by: Brandon Brnich <b-brnich@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 18 ++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++ > 2 files changed, 20 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > index f2b720ed1e4f..e628e748f215 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi > @@ -662,6 +662,24 @@ main_i2c6: i2c@2060000 { > status = "disabled"; > }; > > + vpu0: video-codec@4210000 { > + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; > + reg = <0x00 0x4210000 0x00 0x10000>; > + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&k3_clks 241 2>; > + clock-names = "vcodec"; Binding doesn't allow clock-names [0] [0] Documentation/devicetree/bindings/media/cnm,wave521c.yaml > + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; > + }; > + > + vpu1: video-codec@4220000 { > + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; > + reg = <0x00 0x4220000 0x00 0x10000>; > + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&k3_clks 242 2>; > + clock-names = "vcodec"; > + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; > + }; > + > main_sdhci0: mmc@4f80000 { > compatible = "ti,j721e-sdhci-8bit"; > reg = <0x00 0x04f80000 0x00 0x1000>, > diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi > index 4398c3a463e1..2f633721a0c6 100644 > --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi > @@ -235,6 +235,8 @@ cbass_main: bus@100000 { > ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ > <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ > <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ > + <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ > + <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ > <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ > <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ > <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index f2b720ed1e4f..e628e748f215 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -662,6 +662,24 @@ main_i2c6: i2c@2060000 { status = "disabled"; }; + vpu0: video-codec@4210000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4210000 0x00 0x10000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 241 2>; + clock-names = "vcodec"; + power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; + }; + + vpu1: video-codec@4220000 { + compatible = "ti,j721s2-wave521c", "cnm,wave521c"; + reg = <0x00 0x4220000 0x00 0x10000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 242 2>; + clock-names = "vcodec"; + power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 4398c3a463e1..2f633721a0c6 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -235,6 +235,8 @@ cbass_main: bus@100000 { ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ + <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ + <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
This patch adds support for the Wave521cl on the J784S4-evm. Signed-off-by: Brandon Brnich <b-brnich@ti.com> --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 ++ 2 files changed, 20 insertions(+)