From patchwork Tue Feb 6 08:04:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 13546845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40153C4828D for ; Tue, 6 Feb 2024 08:05:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iMhzk6oKNxm/RJrqz8nuCCm5QVIgJh/DrYsbqeJyY1A=; b=opRGVQBrh4bpDE dlBqkEHLyM/7r9xrwRvZb4lU3CCjxwcL34tj9Du8TcQQHoO0/sFIt/hRibFIJPgEMqEST0erp5kbJ pW9cfZlrSPfqA1P74l1twMTU6qG+PEbmF+CDgVGoZK1T4YWex0CmXf+r7fK9AmiMgqMsUQWwnDS52 OQIATvnKrGtSwJR7H+kGhhVo+OJ2a5TOqpRHAyMaveD3Y+V1GQZkMD4/eRCU2+PWZPdB6A47aJxMB kADyZdyT7COtjPyR4J5Kb6d7oAHyhqedExw5aDN4728+Ltfzn3h+DQ2xxfhOJvmdLoEqcGTuTM0gN LJ13Vbjo9oqNMksODh/A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rXGS3-00000006NTE-1mci; Tue, 06 Feb 2024 08:05:07 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rXGRz-00000006NRX-2iKO for linux-arm-kernel@lists.infradead.org; Tue, 06 Feb 2024 08:05:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1707206703; x=1738742703; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aWrqDxHBsGTji97qijgREMNdfOCrUPOUesPyo61Tvgs=; b=TWQBsn+P/QbO4b5I1pwnoYWJ3ZShXF4l4hWAZb+SlZS5G2og5L3nlvcW /dK+UMdaplTZgPj3DXVKrY98AcdAVOYOosy7QuVifj7DPQtvhLNY0VYW9 ohA3hvWmg20d03LNDOYDahawNPMoMoGR7xqEsb/icjq/INOWHan2PIOvX 1Srx8RLr+hHv0XxlUkblbveiAGDD3grxzRiKNPQgWO1fsSPyHBtfIa5gQ btnDu8XkkD6DBFhqYHOX2hUjZLlIqs/k6M2OIsP2+na+m17CY31uta7Sr ovDSqks3JXJNaJ3dfYXxuU0ZQBj0gvQOM5vJUtddjNkrBc+n7qPWdHeHM g==; X-IronPort-AV: E=Sophos;i="6.05,246,1701126000"; d="scan'208";a="35262220" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 06 Feb 2024 09:05:00 +0100 Received: from steina-w.tq-net.de (steina-w.tq-net.de [10.123.53.25]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 1B49E280084; Tue, 6 Feb 2024 09:05:00 +0100 (CET) From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Fabio Estevam Cc: Alexander Stein , Pengutronix Kernel Team , NXP Linux Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/2] arm64: dts: imx8: Fix lpuart DMA channel order Date: Tue, 6 Feb 2024 09:04:59 +0100 Message-Id: <20240206080459.1741172-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206080459.1741172-1-alexander.stein@ew.tq-group.com> References: <20240206080459.1741172-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240206_000504_010463_942D2EDB X-CRM114-Status: GOOD ( 10.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Bindings say DMA channels are in order Rx, Tx. Adjust the DT nodes accordingly. While at it, use defines for the flags. Signed-off-by: Alexander Stein --- Changes in v2: * Use defines from dt-bindings/dma/fsl-edma.h * Switch DMA channel flags as well arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index a180893ac81e0..cab3468b1875e 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include dma_ipg_clk: clock-dma-ipg { @@ -93,8 +94,8 @@ lpuart0: serial@5a060000 { assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_0>; - dma-names = "tx","rx"; - dmas = <&edma2 9 0 0>, <&edma2 8 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 8 0 FSL_EDMA_RX>, <&edma2 9 0 0>; status = "disabled"; }; @@ -107,8 +108,8 @@ lpuart1: serial@5a070000 { assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_1>; - dma-names = "tx","rx"; - dmas = <&edma2 11 0 0>, <&edma2 10 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 11 0 0>; status = "disabled"; }; @@ -121,8 +122,8 @@ lpuart2: serial@5a080000 { assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_2>; - dma-names = "tx","rx"; - dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>; status = "disabled"; }; @@ -135,8 +136,8 @@ lpuart3: serial@5a090000 { assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_3>; - dma-names = "tx","rx"; - dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; + dma-names = "rx", "tx"; + dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>; status = "disabled"; };