From patchwork Tue Feb 13 23:56:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 13555852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1726AC48260 for ; Tue, 13 Feb 2024 23:57:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=A7n+mdqvLXCdc58MwzEh/LJITT2TwGj3NRacyCdjz1E=; b=tKctMf+CRgEsAV D/p766NriztJsSoUTk1hGLHrJo2UViWbBYathPvPAxYgC526ZL6GLQ9Znl1Nu/bswcuEbv/rReTLY ovSrV2FSyjJftNx+WKNzH2ThOqfQQj08s0B5JB3UwTovlswN2uQCgQgwsQ46ZDupn7a6KRW+v3Yzu soCJUnFJaq8Z4mstq6am1H5ieeN1hWGUaOo8hV7IKk84irrLj6nHiTaM0TFEJN6F7UuquED/xbZrm ocR+V14W7wXRolYrvpIp0+auw0fqbTHduc1+ckmTumt756e1SuqkC0kKe0op2kF/ffQjXtHRyhzvl XdswLkEQ/qhwry6M0DIQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ra2eJ-0000000BJ5f-0GkF; Tue, 13 Feb 2024 23:57:15 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1ra2eC-0000000BJ2G-1BvQ for linux-arm-kernel@lists.infradead.org; Tue, 13 Feb 2024 23:57:09 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 41DNv2Ck082882; Tue, 13 Feb 2024 17:57:02 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1707868622; bh=aL+gNiBwbVuENrnugNe19duI8fO9uL7bvEw/nOCWuDY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=UcuK6sEFuwxrf37QTpu8n630BdjHXFDiEvDujBoCnXj8wXAgHT2bohSEelU+2rLdk vw086FwlUbTL4qVjswehdaT1r7Sk2cLKZsSwGTGQEAsNqBN2pkkGVKKEcNoERuYx1m Uv41L9eh1fWaR/T+ZOfRz1QSDHOGhu+07aE/kYUc= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 41DNv2XO074653 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Feb 2024 17:57:02 -0600 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 13 Feb 2024 17:57:01 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 13 Feb 2024 17:57:01 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41DNv1R9091761; Tue, 13 Feb 2024 17:57:01 -0600 From: Judith Mendez To: Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , , , , Wadim Egorov , Francesco Dolcini Subject: [PATCH v3 5/9] arm64: dts: ti: k3-am62p: Add ITAP/OTAP values for MMC Date: Tue, 13 Feb 2024 17:56:57 -0600 Message-ID: <20240213235701.2438513-6-jm@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240213235701.2438513-1-jm@ti.com> References: <20240213235701.2438513-1-jm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240213_155708_433884_0078592B X-CRM114-Status: UNSURE ( 9.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add OTAP/ITAP values to enable HS400 timing for MMC0 and SDR104 timing for MMC1/MMC2. Remove no-1-8-v property to enable the highest speed mode possible. Update MMC OTAP/ITAP values according to the datasheet [0], refer to Table 7-79 for MMC0 and Table 7-97 for MMC1/MMC2. [0] https://www.ti.com/lit/ds/symlink/am62p.pdf Signed-off-by: Judith Mendez --- Changes since V3: - No change --- arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 44 +++++++++++++++++++++-- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 - 2 files changed, 41 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi index ef1c982a90d8..e43530beb79f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -534,7 +534,21 @@ sdhci0: mmc@fa10000 { clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 57 2>; assigned-clock-parents = <&k3_clks 57 4>; - ti,otap-del-sel-legacy = <0x0>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + ti,clkbuf-sel = <0x7>; + ti,strobe-sel = <0x77>; + ti,trm-icp = <0x8>; + ti,otap-del-sel-legacy = <0x1>; + ti,otap-del-sel-mmc-hs = <0x1>; + ti,otap-del-sel-ddr52 = <0x6>; + ti,otap-del-sel-hs200 = <0x8>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; status = "disabled"; }; @@ -545,7 +559,19 @@ sdhci1: mmc@fa00000 { power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; @@ -556,7 +582,19 @@ sdhci2: mmc@fa20000 { power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; clock-names = "clk_ahb", "clk_xin"; - ti,otap-del-sel-legacy = <0x8>; + bus-width = <4>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 95a0146279b1..8c73587b0b62 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -424,7 +424,6 @@ &sdhci1 { pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; - no-1-8-v; bootph-all; };