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Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 09/13] drm/mediatek: Support alpha blending in Mixer Date: Thu, 15 Feb 2024 18:11:15 +0800 Message-ID: <20240215101119.12629-10-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--7.610000-8.000000 X-TMASE-MatchedRID: x3Ubk3t+gcyc95xD+Eo4wGwbuvhCHs3cIfZjRfGTydgE6M1YtcX6vCtt gmG94b4GsoaiX/cNXYAnOAFYLaUTjQDNPxu11HXjhK8o4aoss8oK3n1SHen81f0TP/kikeqnij7 d44eIVPgo8SIkxCqNtQ2D76bNs2ltQF24kZp9Ww91e7Xbb6Im2greImldQ5BD8cWgFw6wp7MsX2 NvG8rX7UT88A7P9JJ2gAYZl0IbohgfE8yM4pjsDwtuKBGekqUpI/NGWt0UYPABwR31Oy+hyZ1BE 5qIRp0uul8kmJIfbswQ5ZNI9t/XNsLAQYGtsIDO X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--7.610000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: A41FF608559A818A0AEFA4BEB52C7D501EC40F52B3E4200902B2B24E3CD23DF32000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240215_021134_819157_3237CF7E X-CRM114-Status: GOOD ( 12.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support "Pre-multiplied" and "None" blend mode on MediaTek's chips. Before this patch, only the "Coverage" mode is supported. Please refer to the description of the commit "drm/mediatek: Support alpha blending in display driver" for more information. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ethdr.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index 69872b77922eb..e95331c068151 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -35,6 +36,7 @@ #define MIX_SRC_L0_EN BIT(0) #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n)) #define NON_PREMULTI_SOURCE (2 << 12) +#define PREMULTI_SOURCE (3 << 12) #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) #define MIX_FUNC_DCM0 0x120 @@ -153,7 +155,8 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_pending_state *pending = &state->pending; unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x; unsigned int align_width = ALIGN_DOWN(pending->width, 2); - unsigned int alpha_con = 0; + unsigned int mix_con = NON_PREMULTI_SOURCE; + bool replace_src_a = false; dev_dbg(dev, "%s+ idx:%d", __func__, idx); @@ -170,19 +173,28 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, return; } - if (state->base.fb && state->base.fb->format->has_alpha) - alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA; + mix_con |= MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA); - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true, - DEFAULT_9BIT_ALPHA, + if (state->base.pixel_blend_mode != DRM_MODE_BLEND_COVERAGE) + mix_con |= PREMULTI_SOURCE; + + if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || + (state->base.fb && !state->base.fb->format->has_alpha)) { + /* + * Mixer doesn't support CONST_BLD mode, + * use a trick to make the output equivalent + */ + replace_src_a = true; + } + + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA, pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND : MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); - mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx), - 0x1ff); + mtk_ddp_write(cmdq_pkt, mix_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx)); mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, BIT(idx)); }