| Message ID | 20240221073524.20947-4-zajec5@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dts: mediatek: add Cudy WR3000 V1 wireless router | expand |
Il 21/02/24 08:35, Rafał Miłecki ha scritto: > From: Rafał Miłecki <rafal@milecki.pl> > > MT7981 contains on-SoC PIN controller that is also a GPIO provider. > > Signed-off-by: Rafał Miłecki <rafal@milecki.pl> > --- > arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 37 +++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi > index 4feff3d1c5f4..fdd5c22cfc9c 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi > @@ -86,6 +86,43 @@ pwm@10048000 { > #pwm-cells = <2>; > }; > > + pio: pinctrl@11d00000 { > + compatible = "mediatek,mt7981-pinctrl"; > + reg = <0 0x11d00000 0 0x1000>, > + <0 0x11c00000 0 0x1000>, > + <0 0x11c10000 0 0x1000>, > + <0 0x11d20000 0 0x1000>, > + <0 0x11e00000 0 0x1000>, > + <0 0x11e20000 0 0x1000>, > + <0 0x11f00000 0 0x1000>, > + <0 0x11f10000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", > + "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; > + interrupt-controller; > + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&gic>; > + gpio-ranges = <&pio 0 0 56>; > + gpio-controller; > + #gpio-cells = <2>; > + #interrupt-cells = <2>; > + > + mdio-pins { > + mux { That's board specific. MDIO and SPI0 pins can be used as GPIO instead of, respectively, ETH and SPI. Must go to your board devicetree, not here: please move both. Cheers, Angelo > + function = "eth"; > + groups = "smi_mdc_mdio"; > + }; > + }; > + > + spi0-pins { > + mux { > + function = "spi"; > + groups = "spi0", "spi0_wp_hold"; > + }; > + }; > + > + }; > + > clock-controller@15000000 { > compatible = "mediatek,mt7981-ethsys", "syscon"; > reg = <0 0x15000000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 4feff3d1c5f4..fdd5c22cfc9c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -86,6 +86,43 @@ pwm@10048000 { #pwm-cells = <2>; }; + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", + "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + gpio-ranges = <&pio 0 0 56>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + + mdio-pins { + mux { + function = "eth"; + groups = "smi_mdc_mdio"; + }; + }; + + spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + }; + clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>;