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AJvYcCW6QGq8PIgQ+rZ6LdmyqoVftXCPTDCdzfgVXC9xGvBjR4BgxsmLmYxbDq0WVEc5UAN+BnYcNN4me4AxmVUrpEfSbThe3n/E+F0HgWmMpaEIys4nZHM= X-Gm-Message-State: AOJu0Yz2DLDZuhtFtfsJ4Y4ZcJuqCxlnfuwKkUPKu2Sgl3E/3cP3rHQA DrrBN6RjqbeUPjX2FEHBj4rUTn5+i5DKKBFUp8jGPtjkqdRrT18GBB+X++ZKwktFqZdRX2gk5am V X-Google-Smtp-Source: AGHT+IEDPxbGJSvrlZ93JjP4+EdbzDDtWpP2MPh5tJ8fgAQjYG+gZtkJ/x/LoQqtZ7r8SgdKF1ybmQ== X-Received: by 2002:a05:6a21:2d0b:b0:1a0:e59d:1dc4 with SMTP id tw11-20020a056a212d0b00b001a0e59d1dc4mr11149308pzb.11.1708920546850; Sun, 25 Feb 2024 20:09:06 -0800 (PST) Received: from localhost.localdomain ([171.76.86.62]) by smtp.gmail.com with ESMTPSA id d11-20020a170902654b00b001dc6f7e794dsm3023258pln.16.2024.02.25.20.09.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 20:09:06 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v15 01/10] irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA Date: Mon, 26 Feb 2024 09:37:37 +0530 Message-Id: <20240226040746.1396416-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240226040746.1396416-1-apatel@ventanamicro.com> References: <20240226040746.1396416-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240225_200908_897447_3EFA4809 X-CRM114-Status: GOOD ( 12.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Use riscv_intc_aia_irq() as the low-level interrupt handler and print "using AIA" in the INTC boot banner when AIA is available. Fixes: c1be2ae5987a ("irqchip/riscv-intc: Add support for RISC-V AIA") Signed-off-by: Anup Patel --- drivers/irqchip/irq-riscv-intc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index cccb65339982..f87aeab460eb 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -183,7 +183,10 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch return -ENXIO; } - rc = set_handle_irq(&riscv_intc_irq); + if (riscv_isa_extension_available(NULL, SxAIA)) + rc = set_handle_irq(&riscv_intc_aia_irq); + else + rc = set_handle_irq(&riscv_intc_irq); if (rc) { pr_err("failed to set irq handler\n"); return rc; @@ -191,8 +194,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn, struct irq_ch riscv_set_intc_hwnode_fn(riscv_intc_hwnode); - pr_info("%d local interrupts mapped\n", - riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs); + pr_info("%d local interrupts mapped%s\n", + riscv_isa_extension_available(NULL, SxAIA) ? 64 : riscv_intc_nr_irqs, + riscv_isa_extension_available(NULL, SxAIA) ? " using AIA" : ""); if (riscv_intc_custom_nr_irqs) pr_info("%d custom local interrupts mapped\n", riscv_intc_custom_nr_irqs);