diff mbox series

[v2,04/11] i2c: nomadik: simplify IRQ masking logic

Message ID 20240229-mbly-i2c-v2-4-b32ed18c098c@bootlin.com (mailing list archive)
State New, archived
Headers show
Series Add Mobileye EyeQ5 support to the Nomadik I2C controller & use hrtimers for timeouts | expand

Commit Message

Théo Lebrun Feb. 29, 2024, 6:10 p.m. UTC 
IRQ_MASK and I2C_CLEAR_ALL_INTS are redundant. One masks the top three
bits off as reserved, the other one masks the reserved IRQs inside the
u32. Get rid of IRQ_MASK and only use the most restrictive mask.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/i2c/busses/i2c-nomadik.c | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

Comments

Andi Shyti March 2, 2024, 12:39 a.m. UTC | #1 
Hi Theo,

On Thu, Feb 29, 2024 at 07:10:52PM +0100, Théo Lebrun wrote:
> IRQ_MASK and I2C_CLEAR_ALL_INTS are redundant. One masks the top three

if I2C_CLEAR_ALL_INTS is redundant why don't you remove it?

> bits off as reserved, the other one masks the reserved IRQs inside the
> u32. Get rid of IRQ_MASK and only use the most restrictive mask.

Why is IRQ_MASK redundant? What happens if you write in the
reserved bits?

Can you please explain a bit better the change you did?

Thanks,
Andi

> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Théo Lebrun March 4, 2024, 9:46 a.m. UTC | #2 
Hello,

On Sat Mar 2, 2024 at 1:39 AM CET, Andi Shyti wrote:
> On Thu, Feb 29, 2024 at 07:10:52PM +0100, Théo Lebrun wrote:
> > IRQ_MASK and I2C_CLEAR_ALL_INTS are redundant. One masks the top three
>
> if I2C_CLEAR_ALL_INTS is redundant why don't you remove it?

I understand this is unclear. What I meant by redundant is that they are
redundant from one another; one overlaps the other. I'll give a better
commit description for v3. Something like:

   IRQ_MASK and I2C_CLEAR_ALL_INTS both mask available interrupts.
   IRQ_MASK removes top options (bits 29-31). I2C_CLEAR_ALL_INTS
   removes reserved options including top bits. Keep the latter.

   31  29  27  25  23  21  19  17  15  13  11  09  07  05  03  01
     30  28  26  24  22  20  18  16  14  12  10  08  06  04  02  00
   --- IRQ_MASK: --------------------------------------------------
          1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    0 0 0
   --- I2C_CLEAR_ALL_INTS: ----------------------------------------
          1     1 1       1 1 1 1 1                   1 1 1 1 1 1 1
    0 0 0   0 0     0 0 0           0 0 0 0 0 0 0 0 0

    Notice I2C_CLEAR_ALL_INTS is more restrictive than IRQ_MASK.

Is that better?

> > bits off as reserved, the other one masks the reserved IRQs inside the
> > u32. Get rid of IRQ_MASK and only use the most restrictive mask.
>
> Why is IRQ_MASK redundant? What happens if you write in the
> reserved bits?

The wording wasn't correct. Have I answered your
question from the above?

Thanks Andi,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
diff mbox series

Patch

diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index cd511c884f99..80bdf7e42613 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -94,9 +94,6 @@ 
 /* some bits in ICR are reserved */
 #define I2C_CLEAR_ALL_INTS	0x131f007f
 
-/* first three msb bits are reserved */
-#define IRQ_MASK(mask)		(mask & 0x1fffffff)
-
 /* maximum threshold value */
 #define MAX_I2C_FIFO_THRESHOLD	15
 
@@ -249,8 +246,7 @@  static int flush_i2c_fifo(struct nmk_i2c_dev *priv)
  */
 static void disable_all_interrupts(struct nmk_i2c_dev *priv)
 {
-	u32 mask = IRQ_MASK(0);
-	writel(mask, priv->virtbase + I2C_IMSCR);
+	writel(0, priv->virtbase + I2C_IMSCR);
 }
 
 /**
@@ -259,9 +255,7 @@  static void disable_all_interrupts(struct nmk_i2c_dev *priv)
  */
 static void clear_all_interrupts(struct nmk_i2c_dev *priv)
 {
-	u32 mask;
-	mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
-	writel(mask, priv->virtbase + I2C_ICR);
+	writel(I2C_CLEAR_ALL_INTS, priv->virtbase + I2C_ICR);
 }
 
 /**
@@ -468,7 +462,7 @@  static int read_i2c(struct nmk_i2c_dev *priv, u16 flags)
 	else
 		irq_mask |= I2C_IT_MTDWS;
 
-	irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
+	irq_mask &= I2C_CLEAR_ALL_INTS;
 
 	writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,
 	       priv->virtbase + I2C_IMSCR);
@@ -547,7 +541,7 @@  static int write_i2c(struct nmk_i2c_dev *priv, u16 flags)
 	else
 		irq_mask |= I2C_IT_MTDWS;
 
-	irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
+	irq_mask &= I2C_CLEAR_ALL_INTS;
 
 	writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,
 	       priv->virtbase + I2C_IMSCR);
@@ -703,8 +697,8 @@  static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
  */
 static int disable_interrupts(struct nmk_i2c_dev *priv, u32 irq)
 {
-	irq = IRQ_MASK(irq);
-	writel(readl(priv->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
+	irq &= I2C_CLEAR_ALL_INTS;
+	writel(readl(priv->virtbase + I2C_IMSCR) & ~irq,
 	       priv->virtbase + I2C_IMSCR);
 	return 0;
 }