From patchwork Fri Mar 1 01:51:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 13577856 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 614E7C48BF6 for ; Fri, 1 Mar 2024 01:51:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=Qc0swsezh+fmI2vVXj55B7Sruqv5Q0LqSKWYa7d2jJ4=; b=YfuSRwxCer6Vg9 nZYFMFBsHpF+f/qmxiFFiOetDmp04Xno4gcssBlYajFCECAwhI/x+WEA133YYwH4oRg3ulmmvppv2 6uTATpXbt0q4W6ZdIWPXBNyWVuL3qT8UGQDcvih07KCIMjF0AFEw7cMaFCwWCEVOLwEjoQ21KGg86 qCz13kX72i1VQ6fwNsePkOW3+7ynNQP1lQl6tsxzPXEp/ZZlRH3zTc07LzZ/wwpRNvIQPqcrM2e1y TuwLPNMc51LsIWdHs4xVr5u1yCBYKT/R+jF7R6LLUUa+E2C7hICxOVoVhwGRnOslCWecJ61LsKr3F yW7WZWmdMBTfga5+P80Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rfs3Y-0000000FvKh-3I62; Fri, 01 Mar 2024 01:51:24 +0000 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rfs3U-0000000FvJM-3hzs for linux-arm-kernel@lists.infradead.org; Fri, 01 Mar 2024 01:51:22 +0000 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-2204e9290f9so727653fac.2 for ; Thu, 29 Feb 2024 17:51:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1709257879; x=1709862679; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=89qGbY61adiDC0jI07VuVZZvVnnxUhSYInpzriInm0g=; b=J92+1JGdKq+WNRc4On4uRY111lrvwvFXa1Euba991DaAqVR3XiiQd6t7pA9pfs9S1m m0MRTtu4w/lyFCUk1WDWsYjjS1m6NjWhvO6/HkFFNl/qPl7KtGdXbEIFZWg7a0X71AYo wtIXPYCtWZifXdX1yQzGG6T7FZ9yV+bDrTYl+LxoaLyrdWUgVdnFKDghQP72/4XVAl96 hAhz3l0V++OOlZtmBtMAQRBySMEzQH3CiatpR2Z7pX3+27GsOVCLRTmYOniO4FokOwFf uDBCymQsOXB0dVb6sdM3QggrXJiRn5Qcj6JQbqfBD0c9CkBLes3zbDpaXTy9ebyoQsW2 OUTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709257879; x=1709862679; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=89qGbY61adiDC0jI07VuVZZvVnnxUhSYInpzriInm0g=; b=d2s+2cmvhSUOLTHw7Iis3J++8U3O2YMKh/6HgN8CacZbP61gUY80UwkRc/jqGOaq5L 5MmBzQO00lknLRv3RrST88Miz5z7TwmQtAI9G/xMAppT/YgYEp6+/5EyrqikQZ2mFrbJ QgUJU1W8mDeYAJi7INJ33Z6P9lYUhw7N4kaQ8+DVllPZ3NN6/vVtMBL5P16/by0Ii1rs ahszmRmargjSryu/pQJMWSeQisseNA0zEJlhK1GMq+GfHOzoX2+5ICavtV94jWuklaLL XYGsy3OQct3J5c9Eugry+MN0cXcAZYdk8wkLkacaAItD/x3vd10q08832/LnCG85XWfL Wzjg== X-Forwarded-Encrypted: i=1; AJvYcCXvP5FH8HtDq3y5dNwkX1bGgbtrfdnLjswJrkPNPHrl4XeI2GRGXG4T1HFvJ1Cp2EnbsNIfukZcZCXC8/r0xhBMTCfsdD0JpkvneMDSg85a/zE/+/Y= X-Gm-Message-State: AOJu0Yy5UMhe/1I8R6w5+GVb4gNcZ5z6BqaR70068YryO4RVcIT/VKay 6+2lpArW07n0XTY2xLiGq8h8qsq6O/RPIKMhKjz2BqM0vAjUJrnVFA4yNtLB9bM= X-Google-Smtp-Source: AGHT+IG5WbMLsAps1Rv/qERBYELMrznbY8kTNQafWroXqqjZ8VoicEyOJ2ngKFP8bSF/qa4S6YfGXQ== X-Received: by 2002:a05:6870:1652:b0:21e:b096:2494 with SMTP id c18-20020a056870165200b0021eb0962494mr335586oae.50.1709257879454; Thu, 29 Feb 2024 17:51:19 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id ux11-20020a056870af0b00b0021fd54aba16sm754686oab.48.2024.02.29.17.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Feb 2024 17:51:19 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski Cc: Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Tomasz Figa , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/3] clk: samsung: Implement manual PLL control for ARM64 SoCs Date: Thu, 29 Feb 2024 19:51:16 -0600 Message-Id: <20240301015118.30072-1-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240229_175121_008256_AFB8954B X-CRM114-Status: GOOD ( 24.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some ARM64 Exynos chips are capable to control PLL clocks automatically. For those chips, whether the PLL is controlled automatically or manually is chosen in PLL_CON1 register with next bits: [28] ENABLE_AUTOMATIC_CLKGATING [1] MANUAL_PLL_CTRL [0] AUTO_PLL_CTRL The bl2 bootloader sets 0x10000001 value for some PLL_CON1 registers, which means any attempt to control those PLLs manually (e.g. disabling/enabling those PLLs or changing MUX parent clocks) would lead to PLL lock timeout with error message like this: Could not lock PLL ... At the moment, all Samsung clock drivers implement manual clock control. So in order to make it possible to control PLLs, corresponding PLL_CON1 registers should be set to 0x2 first. Some older ARM64 chips don't implement the automatic clock control though. It also might be desirable to configure some PLLs for manual control, while keeping the default configuration for the rest. So it'd convenient to choose this PLL mode for each CMU separately. Introduce .manual_plls field to CMU structure to choose the PLL control mode. Because it'll be initialized with "false" in all existing CMU structures by default, it won't affect any existing clock drivers, allowing for this feature to be enabled gradually when it's needed with no change for the rest of users. In case .manual_plls is set, set PLL_CON1 registers to manual control, akin to what's already done for gate clocks in exynos_arm64_init_clocks(). Of course, PLL_CON1 registers should be added to corresponding struct samsung_cmu_info::clk_regs array to make sure they get initialized. No functional change. This patch adds a feature, but doesn't enable it for any users. Signed-off-by: Sam Protsenko --- Changes in v4: - Turned register checking macros into static functions Changes in v3: - none Changes in v2: - none drivers/clk/samsung/clk-exynos-arm64.c | 56 +++++++++++++++++++------- drivers/clk/samsung/clk.h | 4 ++ 2 files changed, 45 insertions(+), 15 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/clk-exynos-arm64.c index 6fb7194df7ab..bf7de21f329e 100644 --- a/drivers/clk/samsung/clk-exynos-arm64.c +++ b/drivers/clk/samsung/clk-exynos-arm64.c @@ -17,10 +17,17 @@ #include "clk-exynos-arm64.h" +/* PLL register bits */ +#define PLL_CON1_MANUAL BIT(1) + /* Gate register bits */ #define GATE_MANUAL BIT(20) #define GATE_ENABLE_HWACG BIT(28) +/* PLL_CONx_PLL register offsets range */ +#define PLL_CON_OFF_START 0x100 +#define PLL_CON_OFF_END 0x600 + /* Gate register offsets range */ #define GATE_OFF_START 0x2000 #define GATE_OFF_END 0x2fff @@ -38,17 +45,36 @@ struct exynos_arm64_cmu_data { struct samsung_clk_provider *ctx; }; +/* Check if the register offset is a GATE register */ +static bool is_gate_reg(unsigned long off) +{ + return off >= GATE_OFF_START && off <= GATE_OFF_END; +} + +/* Check if the register offset is a PLL_CONx register */ +static bool is_pll_conx_reg(unsigned long off) +{ + return off >= PLL_CON_OFF_START && off <= PLL_CON_OFF_END; +} + +/* Check if the register offset is a PLL_CON1 register */ +static bool is_pll_con1_reg(unsigned long off) +{ + return is_pll_conx_reg(off) && (off & 0xf) == 0x4 && !(off & 0x10); +} + /** * exynos_arm64_init_clocks - Set clocks initial configuration - * @np: CMU device tree node with "reg" property (CMU addr) - * @reg_offs: Register offsets array for clocks to init - * @reg_offs_len: Number of register offsets in reg_offs array + * @np: CMU device tree node with "reg" property (CMU addr) + * @cmu: CMU data * - * Set manual control mode for all gate clocks. + * Set manual control mode for all gate and PLL clocks. */ static void __init exynos_arm64_init_clocks(struct device_node *np, - const unsigned long *reg_offs, size_t reg_offs_len) + const struct samsung_cmu_info *cmu) { + const unsigned long *reg_offs = cmu->clk_regs; + size_t reg_offs_len = cmu->nr_clk_regs; void __iomem *reg_base; size_t i; @@ -60,14 +86,14 @@ static void __init exynos_arm64_init_clocks(struct device_node *np, void __iomem *reg = reg_base + reg_offs[i]; u32 val; - /* Modify only gate clock registers */ - if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END) - continue; - - val = readl(reg); - val |= GATE_MANUAL; - val &= ~GATE_ENABLE_HWACG; - writel(val, reg); + if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) { + writel(PLL_CON1_MANUAL, reg); + } else if (is_gate_reg(reg_offs[i])) { + val = readl(reg); + val |= GATE_MANUAL; + val &= ~GATE_ENABLE_HWACG; + writel(val, reg); + } } iounmap(reg_base); @@ -177,7 +203,7 @@ void __init exynos_arm64_register_cmu(struct device *dev, pr_err("%s: could not enable bus clock %s; err = %d\n", __func__, cmu->clk_name, err); - exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs); + exynos_arm64_init_clocks(np, cmu); samsung_cmu_register_one(np, cmu); } @@ -224,7 +250,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev, __func__, cmu->clk_name, ret); if (set_manual) - exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs); + exynos_arm64_init_clocks(np, cmu); reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(reg_base)) diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index a763309e6f12..a70bd7cce39f 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -330,6 +330,7 @@ struct samsung_clock_reg_cache { * @suspend_regs: list of clock registers to set before suspend * @nr_suspend_regs: count of clock registers in @suspend_regs * @clk_name: name of the parent clock needed for CMU register access + * @manual_plls: Enable manual control for PLL clocks */ struct samsung_cmu_info { const struct samsung_pll_clock *pll_clks; @@ -354,6 +355,9 @@ struct samsung_cmu_info { const struct samsung_clk_reg_dump *suspend_regs; unsigned int nr_suspend_regs; const char *clk_name; + + /* ARM64 Exynos CMUs */ + bool manual_plls; }; struct samsung_clk_provider *samsung_clk_init(struct device *dev,