From patchwork Thu Mar 7 13:33:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 13585583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1CE4C54798 for ; Thu, 7 Mar 2024 13:35:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=NA5oNHNO/jtYYsJe560ydjJq5KRBhGHTbtPnE04zudo=; b=eUq1ZKMnkgENvv LkpxB35Xo7h9TW6goGgo1Fx6SljWlWsgZlkLZWxtlA+7FLfHfzTkuPgxz9TMl1WLrscbD2oZihKZG Mwn2SHeLy373RKIlvWzjj+ig5DuY+H43PL/0ToOwGGMTh6eSeDL6gQ1p5O4i2dvkvfLeIbR4HX2ZZ 7Fu/Wn6uT5byBykkztJSatQV3/RjUXo6LPTLrsCp+xD7G8F2LHFnePEceg9R/01aVkaLyT+tdbD9r mZl69UH4eRhzHDFz7WcAyNed6ioW/qCEzllC6B4OlP/jU9BpKGC/sOaAGb8eVbL2m0a74recX3XP5 c6z7XeRoLZNGQdQasQXw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1riDu1-00000004l3k-3egg; Thu, 07 Mar 2024 13:35:18 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1riDty-00000004l0p-2Epg for linux-arm-kernel@lists.infradead.org; Thu, 07 Mar 2024 13:35:16 +0000 Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4279Ya15007106; Thu, 7 Mar 2024 14:35:08 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=ElfAaGaHRlTpUHfuhu7chh+EcaBsNYx6kELVdLzTaZI=; b=0h +P8tzjmaQAP6ZQE/TbjNxBauUHHWc7Ncle9h89wN40Vk/jRhtGWVSq3xLzL/RIsd +2s2kbuDEUOSDxrYVA6nlMLD6jtdxGsNApo77mZIvsewdCOWbud1C9EWVbikk8dC EhpOwQhJd8F/kiq8aKiZ15gcGo9ofDsPrV4bEix/4wp+abxAYNBNA8PuuzOa1HOF zLpRYKtAzLNOPf/tasDG5lLxg1jyGkYj9gEg9cYtZpOcSjNWUqEWm2RPTpWzczNf ibrYKeP8GPL7+ASGxE+oXSW8jITfkaaOnF1IHDmtvHHw7td7MyN7K1YtbaEhQS3i jRllMwbVuvbpAB3gkYQw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3wmej5dtv0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Mar 2024 14:35:08 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 26C1E40048; Thu, 7 Mar 2024 14:35:05 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E2C7327A500; Thu, 7 Mar 2024 14:34:39 +0100 (CET) Received: from localhost (10.201.22.191) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 7 Mar 2024 14:34:39 +0100 From: Fabrice Gasnier To: CC: , , , , , , Subject: [PATCH v5 05/10] counter: stm32-timer-cnt: add counter prescaler extension Date: Thu, 7 Mar 2024 14:33:01 +0100 Message-ID: <20240307133306.383045-6-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240307133306.383045-1-fabrice.gasnier@foss.st.com> References: <20240307133306.383045-1-fabrice.gasnier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.22.191] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-07_08,2024-03-06_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240307_053514_953220_4FDF7058 X-CRM114-Status: GOOD ( 11.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org There's a prescaler in between the selected input signal used for counting (CK_PSC), and the counter input (CK_CNT). So add the "prescaler" extension to the counter. Reviewed-by: William Breathitt Gray Signed-off-by: Fabrice Gasnier --- Changes in v4: - Add William's Reviewed-by tag Changes in v3: - New patch split from "counter: stm32-timer-cnt: introduce clock signal" --- drivers/counter/stm32-timer-cnt.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c index 65b447b42e75..b969d550e90a 100644 --- a/drivers/counter/stm32-timer-cnt.c +++ b/drivers/counter/stm32-timer-cnt.c @@ -220,11 +220,40 @@ static int stm32_count_enable_write(struct counter_device *counter, return 0; } +static int stm32_count_prescaler_read(struct counter_device *counter, + struct counter_count *count, u64 *prescaler) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 psc; + + regmap_read(priv->regmap, TIM_PSC, &psc); + + *prescaler = psc + 1; + + return 0; +} + +static int stm32_count_prescaler_write(struct counter_device *counter, + struct counter_count *count, u64 prescaler) +{ + struct stm32_timer_cnt *const priv = counter_priv(counter); + u32 psc; + + if (!prescaler || prescaler > MAX_TIM_PSC + 1) + return -ERANGE; + + psc = prescaler - 1; + + return regmap_write(priv->regmap, TIM_PSC, psc); +} + static struct counter_comp stm32_count_ext[] = { COUNTER_COMP_DIRECTION(stm32_count_direction_read), COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write), COUNTER_COMP_CEILING(stm32_count_ceiling_read, stm32_count_ceiling_write), + COUNTER_COMP_COUNT_U64("prescaler", stm32_count_prescaler_read, + stm32_count_prescaler_write), }; static const enum counter_synapse_action stm32_clock_synapse_actions[] = {