From patchwork Wed Apr 3 07:07:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= X-Patchwork-Id: 13615065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E180C6FD1F for ; Wed, 3 Apr 2024 07:18:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BvkW4OD7Si6ng6IaqF3Ibwih9CVvljrsSoSV1BFkufY=; b=I7REZB+aES4SJu 2o+RepNMk/s+4wH7315cLju0YCay30ODP+lTg6m/oAFvkrj79dosKGgRW/NmRjAgUyVuiG1ChnSkU EB/4SjrSSGcVeBIwATqyixOx6x7UzLlMSSLyFkAPkOorVDO95R9VEKhUbuUEPODPngKnGZgDdmw5P mhHdY5fKCzF7E0RENXSW60xXOHQYHvLvG9NzXC05hvCp1jspm2MNW78wCoBliCZwUda9E2NFI/0Al t1mbGTP6A5MOGNyH5iptLjCOGGfZZ6lyegE+ecr5tEvWY34KXOo1y1SlSJFbl/NeJ34BJn2sVkVjU I0JhSGtOHubOW0Zv6ksw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrut9-0000000ESFY-24Mo; Wed, 03 Apr 2024 07:18:27 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrut7-0000000ESDc-0e9u; Wed, 03 Apr 2024 07:18:25 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:CC:To:From:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=b1R7cr/Y69po1CcmKxYFPM6M+QHCkEJfXGlsJ3NaItM=; b=SHoC/ZDI3ANepddxh8TFZdovoq fECv8z19ndStPbYNveC8yy6K8cXLna09LhF1Pboq143r/2gkPO7xrAM8CSeeiXIG5iIMmuwhgAx1N yhCx2vn4akClGy9/6S9ZnMPYlKTe+Sg7ipKeKyUzBoJOHrGa8+IiX3qKv5vjtbp9PhtdmPjutnSrk 7xC7mimjnG9HueMfnsBzdnjjCwUjt0/JjL4ymSDg9RQL/HsanpSliNviAQHbYPfx8RVlDLKwtTJIu ZbbI+hqeTsOGGTRxCJF3VlN4IMjbnU5AdrVXCBqXwgq0AhwGfOehkpmqr6T4qcswbnY6wGjov7aEF k9poJzHg==; Received: from mailgw02.mediatek.com ([216.200.240.185]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrut2-0000000444Y-3Kai; Wed, 03 Apr 2024 07:18:23 +0000 X-UUID: 544951ccf18a11ee96d5dfc950b7243d-20240403 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=b1R7cr/Y69po1CcmKxYFPM6M+QHCkEJfXGlsJ3NaItM=; b=op1QPsi3ILuf0m1Hc2/VhFMv5Sq5Y08rlb2sYUW/scFGgiIzEkPpXX7kHPwp52wBDiN8SmRQ6ammj0ZrND4zYcMx/XJLbcdvz+A+LeTCRPLj6Uvz+xH/k4t/BcpIaaMD9v/O/5SB2YAIwvKPJQTTR0JfJ37pY5Y3Wv7haQa8UYg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:d32daa93-6825-400f-8ee2-86bfcbe84263,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:6f543d0,CLOUDID:a8c2c385-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 544951ccf18a11ee96d5dfc950b7243d-20240403 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1736329896; Wed, 03 Apr 2024 00:18:11 -0700 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 3 Apr 2024 15:07:34 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 3 Apr 2024 15:07:34 +0800 From: Shawn Sung To: Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , AngeloGioacchino Del Regno , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , , , , , , , Jason-JH.Lin , Hsiao Chien Sung Subject: [PATCH v4 7/9] drm/mediatek: Add secure layer config support for ovl Date: Wed, 3 Apr 2024 15:07:30 +0800 Message-ID: <20240403070732.22085-8-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240403070732.22085-1-shawn.sung@mediatek.com> References: <20240403070732.22085-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_081821_586725_33E48ECD X-CRM114-Status: GOOD ( 18.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: "Jason-JH.Lin" Add secure layer config support for ovl. TODO: 1. Move DISP_REG_OVL_SECURE setting to secure world. 2. Change the parameter register address in mtk_ddp_sec_write() from "u32 addr" to "struct cmdq_client_reg *cmdq_reg". Signed-off-by: Jason-JH.Lin Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 ++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 30 +++++++++++++++++++++++-- 3 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index cda0da4848029..b2f59e54c3f4b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -382,6 +382,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, .get_formats = mtk_ovl_get_formats, .get_num_formats = mtk_ovl_get_num_formats, + .get_sec_port = mtk_ovl_get_sec_port, }; static const struct mtk_ddp_comp_funcs ddp_postmask = { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index d2c8fac468798..c4e1b5b8a2e31 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -9,6 +9,7 @@ #include #include #include +#include "mtk_ddp_comp.h" #include "mtk_mdp_rdma.h" #include "mtk_plane.h" @@ -84,6 +85,7 @@ void mtk_ovl_clk_disable(struct device *dev); void mtk_ovl_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +u64 mtk_ovl_get_sec_port(struct mtk_ddp_comp *comp, unsigned int idx); int mtk_ovl_layer_check(struct device *dev, unsigned int idx, struct mtk_plane_state *mtk_state); void mtk_ovl_layer_config(struct device *dev, unsigned int idx, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 279e6193e7975..8cee64495cd04 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -74,6 +74,7 @@ #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n)) #define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04) #define DISP_REG_OVL_HDR_PITCH(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x08) +#define DISP_REG_OVL_SECURE 0x0fc0 #define GMC_THRESHOLD_BITS 16 #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) @@ -218,6 +219,16 @@ void mtk_ovl_crc_read(struct device *dev) mtk_crtc_read_crc(&ovl->crc, ovl->regs); } +u64 mtk_ovl_get_sec_port(struct mtk_ddp_comp *comp, unsigned int idx) +{ + if (comp->id == DDP_COMPONENT_OVL0) + return BIT_ULL(CMDQ_SEC_DISP_OVL0); + else if (comp->id == DDP_COMPONENT_OVL1) + return BIT_ULL(CMDQ_SEC_DISP_OVL1); + + return 0; +} + static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) { struct mtk_disp_ovl *priv = dev_id; @@ -665,8 +676,22 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, DISP_REG_OVL_SRC_SIZE(idx)); mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_OFFSET(idx)); - mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, - DISP_REG_OVL_ADDR(ovl, idx)); + + if (state->pending.is_secure) { + const struct drm_format_info *fmt_info = drm_format_info(fmt); + unsigned int buf_size = (pending->height - 1) * pending->pitch + + pending->width * fmt_info->cpp[0]; + + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, + DISP_REG_OVL_SECURE, BIT(idx)); + mtk_ddp_sec_write(cmdq_pkt, ovl->regs_pa + DISP_REG_OVL_ADDR(ovl, idx), + pending->addr, CMDQ_IWC_H_2_MVA, 0, buf_size, 0); + } else { + mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, + DISP_REG_OVL_SECURE, BIT(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs, + DISP_REG_OVL_ADDR(ovl, idx)); + } if (is_afbc) { mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs, @@ -745,6 +770,7 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev) } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs_pa = res->start; priv->regs = devm_ioremap_resource(dev, res); if (IS_ERR(priv->regs)) { dev_err(dev, "failed to ioremap ovl\n");