| Message ID | 20240403213902.26391-3-james.quinlan@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: brcmstb: Configure appropriate HW CLKREQ# mode | expand |
On Wed, Apr 03, 2024 at 05:38:59PM -0400, Jim Quinlan wrote: > HW initializes an internal bus timeout register to a small value for > debugging convenience. Set this to something reasonable, i.e. in the > vicinity of 10 msec. > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > --- > drivers/pci/controller/pcie-brcmstb.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index f9dd6622fe10..e3480ca4cd57 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -664,6 +664,21 @@ static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) > return 0; > } > > +/* > + * An internal HW bus timer value is set to a small value for debugging > + * convenience. Set this to something reasonable, i.e. somewhere around > + * 10ms. > + */ > +static void brcm_extend_internal_bus_timeout(struct brcm_pcie *pcie, u32 nsec) > +{ > + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */ > + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; > + u32 timeout_us = nsec / 1000; > + > + /* Each unit in timeout register is 1/216,000,000 seconds */ > + writel(216 * timeout_us, pcie->base + REG_OFFSET); > +} > + > /* The controller is capable of serving in both RC and EP roles */ > static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) > { > @@ -1059,6 +1074,9 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) > return -ENODEV; > } > > + /* Extend internal bus timeout to 8ms or so */ > + brcm_extend_internal_bus_timeout(pcie, SZ_8M); The 216*usec is obviously determined by hardware, but the choice of nsec for the interface, and converting to usec internally seems arbitrary; the caller could just easily supply usec. Or do you envision using this interface for timeouts < 1 usec? "SZ_8M" seems a little unusual as a time measurement and doesn't give a hint about the units. It's pretty common to use "8 * USEC_PER_MSEC" or even "8 * NSEC_PER_MSEC" for things like this. But it's fine with me as-is. > if (pcie->gen) > brcm_pcie_set_gen(pcie, pcie->gen); > > -- > 2.17.1 >
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index f9dd6622fe10..e3480ca4cd57 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -664,6 +664,21 @@ static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) return 0; } +/* + * An internal HW bus timer value is set to a small value for debugging + * convenience. Set this to something reasonable, i.e. somewhere around + * 10ms. + */ +static void brcm_extend_internal_bus_timeout(struct brcm_pcie *pcie, u32 nsec) +{ + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */ + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; + u32 timeout_us = nsec / 1000; + + /* Each unit in timeout register is 1/216,000,000 seconds */ + writel(216 * timeout_us, pcie->base + REG_OFFSET); +} + /* The controller is capable of serving in both RC and EP roles */ static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) { @@ -1059,6 +1074,9 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) return -ENODEV; } + /* Extend internal bus timeout to 8ms or so */ + brcm_extend_internal_bus_timeout(pcie, SZ_8M); + if (pcie->gen) brcm_pcie_set_gen(pcie, pcie->gen);
HW initializes an internal bus timeout register to a small value for debugging convenience. Set this to something reasonable, i.e. in the vicinity of 10 msec. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> --- drivers/pci/controller/pcie-brcmstb.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)