diff mbox series

[v2,3/4] coresight: etm4x: Safe access for TRCQCLTR

Message ID 20240412142702.2882478-4-suzuki.poulose@arm.com (mailing list archive)
State New, archived
Headers show
Series coresight: etm4x: Fix CPU idle PM support for ETE | expand

Commit Message

Suzuki K Poulose April 12, 2024, 2:27 p.m. UTC 
ETM4x implements TRCQCLTR only when the Q elements are supported
and the Q element filtering is supported (TRCIDR0.QFILT). Access
to the register otherwise could be fatal. Fix this by tracking the
availability, like the others.

Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
Reported-by: Yabin Cui <yabinc@google.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++++--
 drivers/hwtracing/coresight/coresight-etm4x.h      | 3 +++
 2 files changed, 9 insertions(+), 2 deletions(-)

Comments

Yabin Cui April 12, 2024, 9:28 p.m. UTC | #1 
Tested-by: Yabin Cui <yabinc@google.com>

On Fri, Apr 12, 2024 at 7:27 AM Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> ETM4x implements TRCQCLTR only when the Q elements are supported
> and the Q element filtering is supported (TRCIDR0.QFILT). Access
> to the register otherwise could be fatal. Fix this by tracking the
> availability, like the others.
>
> Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states")
> Reported-by: Yabin Cui <yabinc@google.com>
> Reviewed-by: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++++--
>  drivers/hwtracing/coresight/coresight-etm4x.h      | 3 +++
>  2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index 81df753d8c15..b4b84f2317cd 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1240,6 +1240,8 @@ static void etm4_init_arch_data(void *info)
>         drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
>         /* QSUPP, bits[16:15] Q element support field */
>         drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
> +       if (drvdata->q_support)
> +               drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
>         /* TSSIZE, bits[28:24] Global timestamp size field */
>         drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
>
> @@ -1732,7 +1734,8 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
>         state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
>         state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
>         state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
> -       state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
> +       if (drvdata->q_filt)
> +               state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
>
>         state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
>         state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
> @@ -1862,7 +1865,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>         etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
>         etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
>         etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
> -       etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
> +       if (drvdata->q_filt)
> +               etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
>
>         etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
>         etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 9e430f72bbd6..9e9165f62e81 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -135,6 +135,7 @@
>  #define TRCIDR0_TRCCCI                         BIT(7)
>  #define TRCIDR0_RETSTACK                       BIT(9)
>  #define TRCIDR0_NUMEVENT_MASK                  GENMASK(11, 10)
> +#define TRCIDR0_QFILT                          BIT(14)
>  #define TRCIDR0_QSUPP_MASK                     GENMASK(16, 15)
>  #define TRCIDR0_TSSIZE_MASK                    GENMASK(28, 24)
>
> @@ -954,6 +955,7 @@ struct etmv4_save_state {
>   * @os_unlock:  True if access to management registers is allowed.
>   * @instrp0:   Tracing of load and store instructions
>   *             as P0 elements is supported.
> + * @q_filt:    Q element filtering support, if Q elements are supported.
>   * @trcbb:     Indicates if the trace unit supports branch broadcast tracing.
>   * @trccond:   If the trace unit supports conditional
>   *             instruction tracing.
> @@ -1016,6 +1018,7 @@ struct etmv4_drvdata {
>         bool                            boot_enable;
>         bool                            os_unlock;
>         bool                            instrp0;
> +       bool                            q_filt;
>         bool                            trcbb;
>         bool                            trccond;
>         bool                            retstack;
> --
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 81df753d8c15..b4b84f2317cd 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1240,6 +1240,8 @@  static void etm4_init_arch_data(void *info)
 	drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
 	/* QSUPP, bits[16:15] Q element support field */
 	drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
+	if (drvdata->q_support)
+		drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT);
 	/* TSSIZE, bits[28:24] Global timestamp size field */
 	drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
 
@@ -1732,7 +1734,8 @@  static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
 	state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
 	state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
 	state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
-	state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
+	if (drvdata->q_filt)
+		state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
 
 	state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
 	state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
@@ -1862,7 +1865,8 @@  static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 	etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
 	etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
 	etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
-	etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
+	if (drvdata->q_filt)
+		etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
 
 	etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
 	etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 9e430f72bbd6..9e9165f62e81 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -135,6 +135,7 @@ 
 #define TRCIDR0_TRCCCI				BIT(7)
 #define TRCIDR0_RETSTACK			BIT(9)
 #define TRCIDR0_NUMEVENT_MASK			GENMASK(11, 10)
+#define TRCIDR0_QFILT				BIT(14)
 #define TRCIDR0_QSUPP_MASK			GENMASK(16, 15)
 #define TRCIDR0_TSSIZE_MASK			GENMASK(28, 24)
 
@@ -954,6 +955,7 @@  struct etmv4_save_state {
  * @os_unlock:  True if access to management registers is allowed.
  * @instrp0:	Tracing of load and store instructions
  *		as P0 elements is supported.
+ * @q_filt:	Q element filtering support, if Q elements are supported.
  * @trcbb:	Indicates if the trace unit supports branch broadcast tracing.
  * @trccond:	If the trace unit supports conditional
  *		instruction tracing.
@@ -1016,6 +1018,7 @@  struct etmv4_drvdata {
 	bool				boot_enable;
 	bool				os_unlock;
 	bool				instrp0;
+	bool				q_filt;
 	bool				trcbb;
 	bool				trccond;
 	bool				retstack;