| Message ID | 20240416093648.3620423-1-u-kumar1@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RFC] arm64: dts: ti: k3-j721s2: Add reserved status in msmc node | expand |
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 3cb06a7e4117..f64c8b0780d8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -25,14 +25,17 @@ msmc_ram: sram@70000000 { ranges = <0x0 0x0 0x70000000 0x400000>; atf-sram@0 { + status = "reserved"; reg = <0x0 0x20000>; }; tifs-sram@1f0000 { + status = "reserved"; reg = <0x1f0000 0x10000>; }; l3cache-sram@200000 { + status = "reserved"; reg = <0x200000 0x200000>; }; };
TI K3 SOCs have msmc sram, part of it can be configured as L3 cache depending upon system firmware configuration file. MSMC memory typically host four tenants atf, system firmware (tifs), l3 cache and as sram. Allocation done for atf, tifs and l3-cache is not accessible in address space of OS. Therefore u-boot deletes sysfw and l3cache node before passing DT to OS[0]. But keeping tifs (system firmware) subnode as is. Since TIFS node is not also accessible to OS, I need suggestion for selection of right option. In my view we can handle in two ways 1) delete tifs node as well In this case, only accessible sram will be visible to OS[1] 2) make these nodes (tifs, atf and l3cache) as reserved, so that OS has complete view of memory. This is patch for option 2 to mark atf, l3-cache and tifs as reserved. Also other options are welcome. [0]: https://github.com/u-boot/u-boot/blob/master/arch/arm/mach-k3/common_fdt.c#L67 [1]: https://lore.kernel.org/all/20230420081128.3617214-1-u-kumar1@ti.com/ Signed-off-by: Udit Kumar <u-kumar1@ti.com> --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 3 +++ 1 file changed, 3 insertions(+)