| Message ID | 20240423-usb-phy-gs101-v1-4-ebdcb3ac174d@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | USB31DRD phy support for Google Tensor gs101 (HS & SS) | expand |
Hi André, kernel test robot noticed the following build errors: [auto build test ERROR on a59668a9397e7245b26e9be85d23f242ff757ae8] url: https://github.com/intel-lab-lkp/linux/commits/Andr-Draszik/dt-bindings-phy-samsung-usb3-drd-phy-add-gs101-compatible/20240424-011137 base: a59668a9397e7245b26e9be85d23f242ff757ae8 patch link: https://lore.kernel.org/r/20240423-usb-phy-gs101-v1-4-ebdcb3ac174d%40linaro.org patch subject: [PATCH 4/7] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init() config: arc-randconfig-002-20240424 (https://download.01.org/0day-ci/archive/20240424/202404241238.E14kFCXA-lkp@intel.com/config) compiler: arceb-elf-gcc (GCC) 13.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240424/202404241238.E14kFCXA-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202404241238.E14kFCXA-lkp@intel.com/ All errors (new ones prefixed by >>): drivers/phy/samsung/phy-exynos5-usbdrd.c: In function 'exynos850_usbdrd_utmi_init': >> drivers/phy/samsung/phy-exynos5-usbdrd.c:798:24: error: implicit declaration of function 'FIELD_PREP_CONST' [-Werror=implicit-function-declaration] 798 | reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); | ^~~~~~~~~~~~~~~~ cc1: some warnings being treated as errors vim +/FIELD_PREP_CONST +798 drivers/phy/samsung/phy-exynos5-usbdrd.c 750 751 static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) 752 { 753 void __iomem *regs_base = phy_drd->reg_phy; 754 u32 reg; 755 756 /* 757 * Disable HWACG (hardware auto clock gating control). This will force 758 * QACTIVE signal in Q-Channel interface to HIGH level, to make sure 759 * the PHY clock is not gated by the hardware. 760 */ 761 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 762 reg |= LINKCTRL_FORCE_QACT; 763 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 764 765 /* Start PHY Reset (POR=high) */ 766 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); 767 reg |= CLKRST_PHY_SW_RST; 768 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 769 770 /* Enable UTMI+ */ 771 reg = readl(regs_base + EXYNOS850_DRD_UTMI); 772 reg &= ~(UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP | UTMI_DP_PULLDOWN | 773 UTMI_DM_PULLDOWN); 774 writel(reg, regs_base + EXYNOS850_DRD_UTMI); 775 776 /* Set PHY clock and control HS PHY */ 777 reg = readl(regs_base + EXYNOS850_DRD_HSP); 778 reg |= HSP_EN_UTMISUSPEND | HSP_COMMONONN; 779 writel(reg, regs_base + EXYNOS850_DRD_HSP); 780 781 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ 782 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 783 reg |= LINKCTRL_BUS_FILTER_BYPASS(0xf); 784 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 785 786 reg = readl(regs_base + EXYNOS850_DRD_UTMI); 787 reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID; 788 writel(reg, regs_base + EXYNOS850_DRD_UTMI); 789 790 reg = readl(regs_base + EXYNOS850_DRD_HSP); 791 reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; 792 writel(reg, regs_base + EXYNOS850_DRD_HSP); 793 794 reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); 795 reg &= ~SSPPLLCTL_FSEL; 796 switch (phy_drd->extrefclk) { 797 case EXYNOS5_FSEL_50MHZ: > 798 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); 799 break; 800 case EXYNOS5_FSEL_26MHZ: 801 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); 802 break; 803 case EXYNOS5_FSEL_24MHZ: 804 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); 805 break; 806 case EXYNOS5_FSEL_20MHZ: 807 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); 808 break; 809 case EXYNOS5_FSEL_19MHZ2: 810 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); 811 break; 812 default: 813 dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", 814 phy_drd->extrefclk); 815 break; 816 } 817 writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL); 818 819 /* Power up PHY analog blocks */ 820 reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); 821 reg &= ~HSP_TEST_SIDDQ; 822 writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); 823 824 /* Finish PHY reset (POR=low) */ 825 udelay(10); /* required before doing POR=low */ 826 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); 827 reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST); 828 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 829 udelay(75); /* required after POR=low for guaranteed PHY clock */ 830 831 /* Disable single ended signal out */ 832 reg = readl(regs_base + EXYNOS850_DRD_HSP); 833 reg &= ~HSP_FSV_OUT_EN; 834 writel(reg, regs_base + EXYNOS850_DRD_HSP); 835 } 836
Hi André,
kernel test robot noticed the following build errors:
[auto build test ERROR on a59668a9397e7245b26e9be85d23f242ff757ae8]
url: https://github.com/intel-lab-lkp/linux/commits/Andr-Draszik/dt-bindings-phy-samsung-usb3-drd-phy-add-gs101-compatible/20240424-011137
base: a59668a9397e7245b26e9be85d23f242ff757ae8
patch link: https://lore.kernel.org/r/20240423-usb-phy-gs101-v1-4-ebdcb3ac174d%40linaro.org
patch subject: [PATCH 4/7] phy: exynos5-usbdrd: set ref clk freq in exynos850_usbdrd_utmi_init()
config: hexagon-randconfig-r123-20240424 (https://download.01.org/0day-ci/archive/20240424/202404241533.iud4U7SP-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce: (https://download.01.org/0day-ci/archive/20240424/202404241533.iud4U7SP-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202404241533.iud4U7SP-lkp@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/phy/samsung/phy-exynos5-usbdrd.c:13:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:548:31: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __raw_readb(PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:561:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:37:51: note: expanded from macro '__le16_to_cpu'
#define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
^
In file included from drivers/phy/samsung/phy-exynos5-usbdrd.c:13:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:574:61: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
~~~~~~~~~~ ^
include/uapi/linux/byteorder/little_endian.h:35:51: note: expanded from macro '__le32_to_cpu'
#define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
^
In file included from drivers/phy/samsung/phy-exynos5-usbdrd.c:13:
In file included from include/linux/io.h:14:
In file included from arch/hexagon/include/asm/io.h:328:
include/asm-generic/io.h:585:33: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writeb(value, PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:595:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
~~~~~~~~~~ ^
include/asm-generic/io.h:605:59: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
__raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
~~~~~~~~~~ ^
>> drivers/phy/samsung/phy-exynos5-usbdrd.c:798:10: error: call to undeclared function 'FIELD_PREP_CONST'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7);
^
6 warnings and 1 error generated.
vim +/FIELD_PREP_CONST +798 drivers/phy/samsung/phy-exynos5-usbdrd.c
750
751 static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
752 {
753 void __iomem *regs_base = phy_drd->reg_phy;
754 u32 reg;
755
756 /*
757 * Disable HWACG (hardware auto clock gating control). This will force
758 * QACTIVE signal in Q-Channel interface to HIGH level, to make sure
759 * the PHY clock is not gated by the hardware.
760 */
761 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
762 reg |= LINKCTRL_FORCE_QACT;
763 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
764
765 /* Start PHY Reset (POR=high) */
766 reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
767 reg |= CLKRST_PHY_SW_RST;
768 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
769
770 /* Enable UTMI+ */
771 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
772 reg &= ~(UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP | UTMI_DP_PULLDOWN |
773 UTMI_DM_PULLDOWN);
774 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
775
776 /* Set PHY clock and control HS PHY */
777 reg = readl(regs_base + EXYNOS850_DRD_HSP);
778 reg |= HSP_EN_UTMISUSPEND | HSP_COMMONONN;
779 writel(reg, regs_base + EXYNOS850_DRD_HSP);
780
781 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */
782 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
783 reg |= LINKCTRL_BUS_FILTER_BYPASS(0xf);
784 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
785
786 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
787 reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID;
788 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
789
790 reg = readl(regs_base + EXYNOS850_DRD_HSP);
791 reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL;
792 writel(reg, regs_base + EXYNOS850_DRD_HSP);
793
794 reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL);
795 reg &= ~SSPPLLCTL_FSEL;
796 switch (phy_drd->extrefclk) {
797 case EXYNOS5_FSEL_50MHZ:
> 798 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7);
799 break;
800 case EXYNOS5_FSEL_26MHZ:
801 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6);
802 break;
803 case EXYNOS5_FSEL_24MHZ:
804 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2);
805 break;
806 case EXYNOS5_FSEL_20MHZ:
807 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1);
808 break;
809 case EXYNOS5_FSEL_19MHZ2:
810 reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0);
811 break;
812 default:
813 dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",
814 phy_drd->extrefclk);
815 break;
816 }
817 writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL);
818
819 /* Power up PHY analog blocks */
820 reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST);
821 reg &= ~HSP_TEST_SIDDQ;
822 writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST);
823
824 /* Finish PHY reset (POR=low) */
825 udelay(10); /* required before doing POR=low */
826 reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
827 reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST);
828 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
829 udelay(75); /* required after POR=low for guaranteed PHY clock */
830
831 /* Disable single ended signal out */
832 reg = readl(regs_base + EXYNOS850_DRD_HSP);
833 reg &= ~HSP_FSV_OUT_EN;
834 writel(reg, regs_base + EXYNOS850_DRD_HSP);
835 }
836
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index d69187c22613..0f9078689856 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -155,6 +155,9 @@ #define CLKRST_PORT_RST BIT(1) #define CLKRST_PHY_SW_RST BIT(3) +#define EXYNOS850_DRD_SSPPLLCTL 0x30 +#define SSPPLLCTL_FSEL GENMASK(2, 0) + #define EXYNOS850_DRD_UTMI 0x50 #define UTMI_FORCE_SLEEP BIT(0) #define UTMI_FORCE_SUSPEND BIT(1) @@ -788,6 +791,31 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; writel(reg, regs_base + EXYNOS850_DRD_HSP); + reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); + reg &= ~SSPPLLCTL_FSEL; + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); + break; + case EXYNOS5_FSEL_26MHZ: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); + break; + case EXYNOS5_FSEL_24MHZ: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); + break; + case EXYNOS5_FSEL_20MHZ: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); + break; + case EXYNOS5_FSEL_19MHZ2: + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); + break; + default: + dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", + phy_drd->extrefclk); + break; + } + writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL); + /* Power up PHY analog blocks */ reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); reg &= ~HSP_TEST_SIDDQ;
While commit 255ec3879dd4 ("phy: exynos5-usbdrd: Add 26MHz ref clk support") correctly states that CLKRSTCTRL[7:5] doesn't need to be set on modern Exynos platforms, SSPPLLCTL[2:0] should be programmed with the frequency of the reference clock for the USB2.0 phy. Do so. Fixes: 691525074db9 ("phy: exynos5-usbdrd: Add Exynos850 support") Signed-off-by: André Draszik <andre.draszik@linaro.org> --- Feel free to drop the Fixes: if you think that is unwarranted here. --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)