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[31.11.218.106]) by smtp.gmail.com with ESMTPSA id s17-20020a1709067b9100b00a51bf5932aesm6900880ejo.28.2024.04.23.04.03.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Apr 2024 04:03:14 -0700 (PDT) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Florian Fainelli , Hauke Mehrtens Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= Subject: [PATCH 1/2] ARM: dts: BCM5301X: Drop ranges mapping from AXI bus Date: Tue, 23 Apr 2024 13:02:37 +0200 Message-Id: <20240423110238.32148-1-zajec5@gmail.com> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240423_040316_831553_224C904F X-CRM114-Status: GOOD ( 11.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Rafał Miłecki Limiting addresses to 0x18000000 + 0x100000 disallowed describing some devices (e.g. PCIe controllers). Signed-off-by: Rafał Miłecki Reviewed-by: Linus Walleij --- arch/arm/boot/dts/broadcom/bcm-ns.dtsi | 146 ++++++++++++------------- 1 file changed, 73 insertions(+), 73 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi index d0d5f7e52a91..7c8ee2df538f 100644 --- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi @@ -95,7 +95,7 @@ L2: cache-controller@22000 { axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; - ranges = <0x00000000 0x18000000 0x00100000>; + ranges; #address-cells = <1>; #size-cells = <1>; @@ -103,77 +103,77 @@ axi@18000000 { interrupt-map-mask = <0x000fffff 0xffff>; interrupt-map = /* ChipCommon */ - <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <0x18000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, /* Switch Register Access Block */ - <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0x18007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, /* PCIe Controller 0 */ - <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0x18012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0x18012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <0x18012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0x18012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0x18012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0x18012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, /* PCIe Controller 1 */ - <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <0x18013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <0x18013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <0x18013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <0x18013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <0x18013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0x18013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, /* PCIe Controller 2 */ - <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <0x18014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x18014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0x18014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <0x18014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <0x18014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <0x18014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* USB 2.0 Controller */ - <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <0x18021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* USB 3.0 Controller */ - <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <0x18023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, /* Ethernet Controller 0 */ - <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <0x18024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, /* Ethernet Controller 1 */ - <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0x18025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, /* Ethernet Controller 2 */ - <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0x18026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* Ethernet Controller 3 */ - <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0x18027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* NAND Controller */ - <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - - chipcommon: chipcommon@0 { - reg = <0x00000000 0x1000>; + <0x18028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <0x18028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <0x18028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <0x18028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <0x18028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0x18028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0x18028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x18028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon: chipcommon@18000000 { + reg = <0x18000000 0x1000>; gpio-controller; #gpio-cells = <2>; @@ -181,29 +181,29 @@ chipcommon: chipcommon@0 { #interrupt-cells = <2>; }; - pcie0: pcie@12000 { - reg = <0x00012000 0x1000>; + pcie0: pcie@18012000 { + reg = <0x18012000 0x1000>; #address-cells = <3>; #size-cells = <2>; }; - pcie1: pcie@13000 { - reg = <0x00013000 0x1000>; + pcie1: pcie@18013000 { + reg = <0x18013000 0x1000>; #address-cells = <3>; #size-cells = <2>; }; - pcie2: pcie@14000 { - reg = <0x00014000 0x1000>; + pcie2: pcie@18014000 { + reg = <0x18014000 0x1000>; #address-cells = <3>; #size-cells = <2>; }; - usb2: usb2@21000 { - reg = <0x00021000 0x1000>; + usb2: usb2@18021000 { + reg = <0x18021000 0x1000>; #address-cells = <1>; #size-cells = <1>; @@ -211,9 +211,9 @@ usb2: usb2@21000 { interrupt-parent = <&gic>; - ehci: usb@21000 { + ehci: usb@18021000 { compatible = "generic-ehci"; - reg = <0x00021000 0x1000>; + reg = <0x18021000 0x1000>; interrupts = ; phys = <&usb2_phy>; @@ -231,9 +231,9 @@ ehci_port2: port@2 { }; }; - ohci: usb@22000 { + ohci: usb@18022000 { compatible = "generic-ohci"; - reg = <0x00022000 0x1000>; + reg = <0x18022000 0x1000>; interrupts = ; #address-cells = <1>; @@ -251,8 +251,8 @@ ohci_port2: port@2 { }; }; - usb3: usb3@23000 { - reg = <0x00023000 0x1000>; + usb3: usb3@18023000 { + reg = <0x18023000 0x1000>; #address-cells = <1>; #size-cells = <1>; @@ -260,9 +260,9 @@ usb3: usb3@23000 { interrupt-parent = <&gic>; - xhci: usb@23000 { + xhci: usb@18023000 { compatible = "generic-xhci"; - reg = <0x00023000 0x1000>; + reg = <0x18023000 0x1000>; interrupts = ; phys = <&usb3_phy>; phy-names = "usb"; @@ -277,8 +277,8 @@ xhci_port1: port@1 { }; }; - gmac0: ethernet@24000 { - reg = <0x24000 0x800>; + gmac0: ethernet@18024000 { + reg = <0x18024000 0x800>; phy-mode = "internal"; fixed-link { @@ -287,8 +287,8 @@ fixed-link { }; }; - gmac1: ethernet@25000 { - reg = <0x25000 0x800>; + gmac1: ethernet@18025000 { + reg = <0x18025000 0x800>; phy-mode = "internal"; fixed-link { @@ -297,8 +297,8 @@ fixed-link { }; }; - gmac2: ethernet@26000 { - reg = <0x26000 0x800>; + gmac2: ethernet@18026000 { + reg = <0x18026000 0x800>; phy-mode = "internal"; fixed-link { @@ -307,7 +307,7 @@ fixed-link { }; }; - gmac3: ethernet@27000 { + gmac3: ethernet@18027000 { reg = <0x27000 0x800>; }; };