From patchwork Tue Apr 23 12:33:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amelie Delaunay X-Patchwork-Id: 13639987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56F1AC4345F for ; Tue, 23 Apr 2024 12:36:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wrJ8NCtJ98D09um1AM+LnT064lIif7+x5kZmoMiYku8=; b=T0/q9itk1b6G4U jAeiqGDhosqPCtG22JGWMDbsaSCkLJoIIMo7/EnMlQNrQUFXW9LXaIAm4h+GSpo7IRhsYBhGiJiLj sOVRx9BwbmpAE3DQSRO9B7wjKDCUGjKeO0fRxacE14lg5Ch9NHzdYYovQnrIL8WYFpqspCfz98Cob ZAL1iBsSuaI2ZjlT/zUOP25SCA2LLGL7PR2h1bpP6CY1XuYqxtQbbPcdt6W9d5kamumzE2sBiFUZd T3ntUtYCaFtckTBE08BsadkO6DvP/yhhXBADqNAIhlP+ZfUqa3TAnQXazB2GrctQ30c8u5PaPIQV+ i6Ix9v2vx88TTjTtojhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rzFOB-0000000HPzA-1iGu; Tue, 23 Apr 2024 12:36:47 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rzFNs-0000000HPmg-0AgV for linux-arm-kernel@lists.infradead.org; Tue, 23 Apr 2024 12:36:30 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 43N8H3ql011919; Tue, 23 Apr 2024 14:36:20 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=qJAQvcReYkKykfb7YDV3qlgrNFyxPWTmX6W3WAi2TpY=; b=M4 ASwh+U++lKh7IKpiPgXCubMEzEncw0phz8JPRWjC540afiqXaxn9iNsJ7Ghz6t0H mvEBPDnig3rAqrxT5WxzHCVN+tRRZ/U23m9WqlE7/q3+ws/pTmONXYFZDO6aHm4A 5kV0+UO4rxkDH/JEG2XRHsu9rPI1XJSw4KadJys8gMCp1OyYLNR7vhHuwF6KFRI6 Y19OJDYlU3bwbWkC2ftw08bcQD17FQA4S4TTYJOjDjzfOTgC2fQS3NJz0JVRoV3X pPK3Z9HSUsKa//LHPjM9yVTWvvueCNA0cx9L3t2X65659FKsdBFOPapNs25em+Qd Pr2YsDAkH47CJRPhrL7w== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3xm4kb3dfp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 23 Apr 2024 14:36:20 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 3FA8A40047; Tue, 23 Apr 2024 14:36:16 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6851921A237; Tue, 23 Apr 2024 14:35:32 +0200 (CEST) Received: from localhost (10.48.86.143) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 23 Apr 2024 14:35:32 +0200 From: Amelie Delaunay To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , , Amelie Delaunay Subject: [PATCH 11/12] dmaengine: stm32-dma3: defer channel registration to specify channel name Date: Tue, 23 Apr 2024 14:33:01 +0200 Message-ID: <20240423123302.1550592-12-amelie.delaunay@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240423123302.1550592-1-amelie.delaunay@foss.st.com> References: <20240423123302.1550592-1-amelie.delaunay@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.86.143] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-23_11,2024-04-23_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240423_053628_433188_D07ADA5D X-CRM114-Status: GOOD ( 14.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On STM32 DMA3, channels can be reserved, so they are non available for Linux. This non-availability creates a mismatch between dma_chan id and DMA3 channel id. Use dma_async_device_channel_register() to register the channels after controller registration and change the default channel name, so that it can match the name in the Reference Manual and ease requesting a channel thanks to its name. Signed-off-by: Amelie Delaunay --- drivers/dma/stm32/stm32-dma3.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/dma/stm32/stm32-dma3.c b/drivers/dma/stm32/stm32-dma3.c index f15cc0129fc7..b6d8afd5ed34 100644 --- a/drivers/dma/stm32/stm32-dma3.c +++ b/drivers/dma/stm32/stm32-dma3.c @@ -1723,9 +1723,6 @@ static int stm32_dma3_probe(struct platform_device *pdev) chan->fifo_size = get_chan_hwcfg(i, G_FIFO_SIZE(i), hwcfgr); /* If chan->fifo_size > 0 then half of the fifo size, else no burst when no FIFO */ chan->max_burst = (chan->fifo_size) ? (1 << (chan->fifo_size + 1)) / 2 : 0; - chan->vchan.desc_free = stm32_dma3_chan_vdesc_free; - - vchan_init(&chan->vchan, dma_dev); } ret = dmaenginem_async_device_register(dma_dev); @@ -1733,14 +1730,26 @@ static int stm32_dma3_probe(struct platform_device *pdev) goto err_clk_disable; for (i = 0; i < ddata->dma_channels; i++) { + char name[12]; + if (chan_reserved & BIT(i)) continue; + chan = &ddata->chans[i]; + snprintf(name, sizeof(name), "dma%dchan%d", ddata->dma_dev.dev_id, chan->id); + + chan->vchan.desc_free = stm32_dma3_chan_vdesc_free; + vchan_init(&chan->vchan, dma_dev); + + ret = dma_async_device_channel_register(&ddata->dma_dev, &chan->vchan.chan, name); + if (ret) { + dev_err_probe(&pdev->dev, ret, "Failed to register channel %s\n", name); + goto err_clk_disable; + } + ret = platform_get_irq(pdev, i); if (ret < 0) goto err_clk_disable; - - chan = &ddata->chans[i]; chan->irq = ret; ret = devm_request_irq(&pdev->dev, chan->irq, stm32_dma3_chan_irq, 0,