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AJvYcCVsnTFg4SV7AubeA0HV4nTKwaM2+kLQzufRQq3djYHvVE6EvrAn7iUUVKFXWxzv5AoTs98N/Sev9L6iKyZs6u9JpZO7h1QNT9ZqmN3txX592g08CVg= X-Gm-Message-State: AOJu0YyvRxOiTWPy5PHik5bev12VbzOXTXoa+MjXUxV5LVcBYjJc6+Pw F16yXhXG4LMlJzgRDg9Hr1pYJtFJoKOfrCN5+kNP1rxXHhC821DQ X-Google-Smtp-Source: AGHT+IHFsfd1jX7pOazkuawT08Lov2Gli5HIokS31G862grOZlEAa7XZMq3oEvPkdYQNBTJt+IaKqg== X-Received: by 2002:a17:902:6bc4:b0:1e8:b7fc:7f85 with SMTP id m4-20020a1709026bc400b001e8b7fc7f85mr3033829plt.31.1713984672683; Wed, 24 Apr 2024 11:51:12 -0700 (PDT) Received: from stbirv-lnx-1.igp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id u8-20020a170902e5c800b001e425d86ad9sm12268728plf.151.2024.04.24.11.51.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 11:51:12 -0700 (PDT) From: Doug Berger To: Linus Walleij , Bartosz Golaszewski Cc: Phil Elwell , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Doug Berger Subject: [PATCH 2/3] gpio: of: support gpio-ranges for multiple gpiochip devices Date: Wed, 24 Apr 2024 11:50:38 -0700 Message-Id: <20240424185039.1707812-3-opendmb@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424185039.1707812-1-opendmb@gmail.com> References: <20240424185039.1707812-1-opendmb@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240424_115118_013424_AAC89D5E X-CRM114-Status: GOOD ( 17.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some drivers (e.g. gpio-mt7621 and gpio-brcmstb) have multiple gpiochip banks within a single device. Unfortunately, the gpio-ranges property of the device node was being applied to every gpiochip of the device with device relative GPIO offset values rather than gpiochip relative GPIO offset values. This commit makes use of the gpio_chip offset value which can be non-zero for such devices to split the device node gpio-ranges property into GPIO offset ranges that can be applied to each of the relevant gpiochips of the device. Signed-off-by: Doug Berger Acked-by: Florian Fainelli --- drivers/gpio/gpiolib-of.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index cb0cefaec37e..d75f6ee37028 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -1037,7 +1037,7 @@ static int of_gpiochip_add_pin_range(struct gpio_chip *chip) struct of_phandle_args pinspec; struct pinctrl_dev *pctldev; struct device_node *np; - int index = 0, ret; + int index = 0, ret, trim; const char *name; static const char group_names_propname[] = "gpio-ranges-group-names"; struct property *group_names; @@ -1059,7 +1059,14 @@ static int of_gpiochip_add_pin_range(struct gpio_chip *chip) if (!pctldev) return -EPROBE_DEFER; + /* Ignore ranges outside of this GPIO chip */ + if (pinspec.args[0] >= (chip->offset + chip->ngpio)) + continue; + if (pinspec.args[0] + pinspec.args[2] <= chip->offset) + continue; + if (pinspec.args[2]) { + /* npins != 0: linear range */ if (group_names) { of_property_read_string_index(np, group_names_propname, @@ -1070,7 +1077,19 @@ static int of_gpiochip_add_pin_range(struct gpio_chip *chip) break; } } - /* npins != 0: linear range */ + + /* Trim the range to fit this GPIO chip */ + if (chip->offset > pinspec.args[0]) { + trim = chip->offset - pinspec.args[0]; + pinspec.args[2] -= trim; + pinspec.args[1] += trim; + pinspec.args[0] = 0; + } else { + pinspec.args[0] -= chip->offset; + } + if ((pinspec.args[0] + pinspec.args[2]) > chip->ngpio) + pinspec.args[2] = chip->ngpio - pinspec.args[0]; + ret = gpiochip_add_pin_range(chip, pinctrl_dev_get_devname(pctldev), pinspec.args[0],