@@ -2157,6 +2157,99 @@ watchdog1: watchdog@2210000 {
assigned-clock-parents = <&k3_clks 253 5>;
};
+ /*
+ * The following RTI instances are coupled with MCU R5Fs, c7x and
+ * GPU so keeping them reserved as these will be used by their
+ * respective firmware
+ */
+ watchdog15: watchdog@22f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x22f0000 0x00 0x100>;
+ clocks = <&k3_clks 257 1>;
+ power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 257 1>;
+ assigned-clock-parents = <&k3_clks 257 5>;
+ /* reserved for GPU */
+ status = "reserved";
+ };
+
+ watchdog16: watchdog@2300000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2300000 0x00 0x100>;
+ clocks = <&k3_clks 256 1>;
+ power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 256 1>;
+ assigned-clock-parents = <&k3_clks 256 5>;
+ /* reserved for C7X */
+ status = "reserved";
+ };
+
+ watchdog24: watchdog@2380000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2380000 0x00 0x100>;
+ clocks = <&k3_clks 254 1>;
+ power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 254 1>;
+ assigned-clock-parents = <&k3_clks 254 5>;
+ /* reserved for C66X_0 */
+ status = "reserved";
+ };
+
+ watchdog25: watchdog@2390000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x2390000 0x00 0x100>;
+ clocks = <&k3_clks 255 1>;
+ power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 255 1>;
+ assigned-clock-parents = <&k3_clks 255 5>;
+ /* reserved for C66X_1 */
+ status = "reserved";
+ };
+
+ watchdog28: watchdog@23c0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23c0000 0x00 0x100>;
+ clocks = <&k3_clks 258 1>;
+ power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 258 1>;
+ assigned-clock-parents = <&k3_clks 258 5>;
+ /* reserved for MAIN_R5F0_0 */
+ status = "reserved";
+ };
+
+ watchdog29: watchdog@23d0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23d0000 0x00 0x100>;
+ clocks = <&k3_clks 259 1>;
+ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 259 1>;
+ assigned-clock-parents = <&k3_clks 259 5>;
+ /* reserved for MAIN_R5F0_1 */
+ status = "reserved";
+ };
+
+ watchdog30: watchdog@23e0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23e0000 0x00 0x100>;
+ clocks = <&k3_clks 260 1>;
+ power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 260 1>;
+ assigned-clock-parents = <&k3_clks 260 5>;
+ /* reserved for MAIN_R5F1_0 */
+ status = "reserved";
+ };
+
+ watchdog31: watchdog@23f0000 {
+ compatible = "ti,j7-rti-wdt";
+ reg = <0x00 0x23f0000 0x00 0x100>;
+ clocks = <&k3_clks 261 1>;
+ power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
+ assigned-clocks = <&k3_clks 261 1>;
+ assigned-clock-parents = <&k3_clks 261 5>;
+ /* reserved for MAIN_R5F1_1 */
+ status = "reserved";
+ };
+
main_r5fss0: r5fss@5c00000 {
compatible = "ti,j721e-r5fss";
ti,cluster-mode = <1>;