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AJvYcCUoUYcdGiM62KM+agO8uc6LdKxroXlZ4ZvOHDsMXYDiEXiQ3lC9JJUpsk3itQ2kRfyGeI84htSQiekjDSSsj+KHw12bHKZGV8a406te6AJemgvpXXs= X-Gm-Message-State: AOJu0YxnM8wgXYHjBfqHoGyqUPrA0Jlngb7ieiasXXj6x5ED+Wg0fCHH Kvv58qL8uJqRIbb0JqqXgpExP34ZpsKOS/+MUZ1GrAuodjwVusSTu2+OQ46FKQ== X-Google-Smtp-Source: AGHT+IE8IGwWKDE8w65mqrsUHZCWFhQYSBQsWdqW2ncfFU1qhQ9LU47X0Hj6sRPRPpb9Jccy3pViug== X-Received: by 2002:a05:6a20:d80f:b0:1af:3d3f:83f1 with SMTP id iv15-20020a056a20d80f00b001af3d3f83f1mr5737629pzb.44.1714384450196; Mon, 29 Apr 2024 02:54:10 -0700 (PDT) Received: from treapking.tpe.corp.google.com ([2401:fa00:1:10:38e5:4a2b:ec4a:2ec9]) by smtp.gmail.com with ESMTPSA id c7-20020a056a000ac700b006eb0027f2b8sm18932083pfl.9.2024.04.29.02.54.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Apr 2024 02:54:10 -0700 (PDT) From: Pin-yen Lin To: Matthias Brugger , AngeloGioacchino Del Regno Cc: devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), =?utf-8?q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), Hsin-Te Yuan , Pin-yen Lin Subject: [PATCH] arm64: dts: mediatek: mt8192-asurada: Add off-on-delay-us for pp3300_mipibrdg Date: Mon, 29 Apr 2024 17:53:31 +0800 Message-ID: <20240429095333.3585438-1-treapking@chromium.org> X-Mailer: git-send-email 2.44.0.769.g3c40516874-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240429_025412_639975_876D9AC4 X-CRM114-Status: GOOD ( 10.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Set off-on-delay-us to 500000 us for pp3300_mipibrdg to make sure it complies with the panel sequence. Explicit configuration on the regulator node is required because mt8192-asurada uses the same power supply for the panel and the anx7625 DP bridge. So powering on/off the DP bridge could break the power sequence requirement for the panel. Fixes: f9f00b1f6b9b ("arm64: dts: mediatek: asurada: Add display regulators") Signed-off-by: Pin-yen Lin Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 7a704246678f..08d71ddf3668 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -147,6 +147,7 @@ pp3300_mipibrdg: regulator-3v3-mipibrdg { regulator-boot-on; gpio = <&pio 127 GPIO_ACTIVE_HIGH>; vin-supply = <&pp3300_g>; + off-on-delay-us = <500000>; }; /* separately switched 3.3V power rail */