| Message ID | 20240429111537.2369227-3-peter.griffin@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable UFS on gs101 / Pixel 6 (Oriole) | expand |
On 29/04/2024 13:15, Peter Griffin wrote: > This has some configuration bits such as sharability that > are required by UFS. > > Signed-off-by: Peter Griffin <peter.griffin@linaro.org> > Reviewed-by: André Draszik <andre.draszik@linaro.org> > --- > arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > index 38ac4fb1397e..09044deede63 100644 > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi > @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 { > clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; > }; Does not apply anymore, please rebase. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 38ac4fb1397e..09044deede63 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 { clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card"; }; + sysreg_hsi2: syscon@14420000 { + compatible = "google,gs101-hsi2-sysreg", "syscon"; + reg = <0x14420000 0x10000>; + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>; + }; + pinctrl_hsi2: pinctrl@14440000 { compatible = "google,gs101-pinctrl"; reg = <0x14440000 0x00001000>;