| Message ID | 20240429120932.11456-2-r-gunasekaran@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add USB support for J722S EVM | expand |
On 29/04/2024 15:09, Ravi Gunasekaran wrote: > Add SERDES0 and its wrapper description to support USB3 > and SGMII interfaces. > > Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi > index c75744edb143..beba5a3ea6cc 100644 > --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi > @@ -9,6 +9,7 @@ > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/soc/ti,sci_pm_domain.h> > +#include <dt-bindings/phy/phy-ti.h> > > #include "k3-am62p5.dtsi" > > @@ -75,6 +76,50 @@ > <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, > <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; > }; > + > + serdes_refclk: clock-cmnrefclk { What could be the generic name here? > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; > + }; > + > + serdes_wiz0: wiz@f000000 { Should generic name be phy? > + compatible = "ti,am64-wiz-10g"; > + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; > + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; > + num-lanes = <1>; > + #reset-cells = <1>; > + #clock-cells = <1>; > + > + assigned-clocks = <&k3_clks 279 1>; > + assigned-clock-parents = <&k3_clks 279 5>; > + > + serdes0: serdes@f000000 { here too? > + compatible = "ti,j721e-serdes-10g"; > + reg = <0x0f000000 0x00010000>; > + reg-names = "torrent_phy"; > + resets = <&serdes_wiz0 0>; > + reset-names = "torrent_reset"; > + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; > + clock-names = "refclk", "phy_en_refclk"; > + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, > + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, > + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; > + assigned-clock-parents = <&k3_clks 279 1>, > + <&k3_clks 279 1>, > + <&k3_clks 279 1>; > + #address-cells = <1>; > + #size-cells = <0>; > + #clock-cells = <1>; > + > + status = "disabled"; /* Needs lane config */ > + }; > + }; > }; > > /* Main domain overrides */ > @@ -83,6 +128,15 @@ > ti,interrupt-ranges = <7 71 21>; > }; > > +&main_conf { > + serdes0_ln_ctrl: mux-controller@4080 { > + compatible = "reg-mux"; > + reg = <0x4080 0x4>; > + #mux-control-cells = <1>; > + mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ > + }; > +}; > + > &oc_sram { > reg = <0x00 0x70000000 0x00 0x40000>; > ranges = <0x00 0x00 0x70000000 0x40000>;
On 5/8/24 5:29 PM, Roger Quadros wrote: > > > On 29/04/2024 15:09, Ravi Gunasekaran wrote: >> Add SERDES0 and its wrapper description to support USB3 >> and SGMII interfaces. >> >> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++ >> 1 file changed, 54 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi >> index c75744edb143..beba5a3ea6cc 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi >> @@ -9,6 +9,7 @@ >> #include <dt-bindings/interrupt-controller/irq.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/soc/ti,sci_pm_domain.h> >> +#include <dt-bindings/phy/phy-ti.h> >> >> #include "k3-am62p5.dtsi" >> >> @@ -75,6 +76,50 @@ >> <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, >> <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; >> }; >> + >> + serdes_refclk: clock-cmnrefclk { > > What could be the generic name here? > How about phy-clk or serdes-clk? I searched for "fixed-clock" and wide range of naming conventions is followed. >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <0>; >> + }; >> + >> + serdes_wiz0: wiz@f000000 { > > Should generic name be phy? Since serdes is used for both USB and PCIe, I can go with "phy". > >> + compatible = "ti,am64-wiz-10g"; >> + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; >> + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; >> + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; >> + num-lanes = <1>; >> + #reset-cells = <1>; >> + #clock-cells = <1>; >> + >> + assigned-clocks = <&k3_clks 279 1>; >> + assigned-clock-parents = <&k3_clks 279 5>; >> + >> + serdes0: serdes@f000000 { > > here too? I could use "phy" here as well. https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/sa8775p.dtsi#L1853 https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/renesas/r8a779f0.dtsi#L563 > >> + compatible = "ti,j721e-serdes-10g"; [...] >
On 08/05/2024 15:34, Ravi Gunasekaran wrote: > > > On 5/8/24 5:29 PM, Roger Quadros wrote: >> >> >> On 29/04/2024 15:09, Ravi Gunasekaran wrote: >>> Add SERDES0 and its wrapper description to support USB3 >>> and SGMII interfaces. >>> >>> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> >>> --- >>> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++ >>> 1 file changed, 54 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi >>> index c75744edb143..beba5a3ea6cc 100644 >>> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi >>> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi >>> @@ -9,6 +9,7 @@ >>> #include <dt-bindings/interrupt-controller/irq.h> >>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>> #include <dt-bindings/soc/ti,sci_pm_domain.h> >>> +#include <dt-bindings/phy/phy-ti.h> >>> >>> #include "k3-am62p5.dtsi" >>> >>> @@ -75,6 +76,50 @@ >>> <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, >>> <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; >>> }; >>> + >>> + serdes_refclk: clock-cmnrefclk { >> >> What could be the generic name here? >> > > How about phy-clk or serdes-clk? > I searched for "fixed-clock" and wide range of naming conventions is followed. We shouldn't encode the clock function in the name. How about just clk-<n> ? where <n> is an integer starting from 0 for such fixed-clocks on the platform? e.g. from arch/arm64/boot/dts/ti/k3-am62p5-sk.dts tlv320_mclk: clk-0 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <12288000>; }; > >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <0>; >>> + }; >>> + >>> + serdes_wiz0: wiz@f000000 { >> >> Should generic name be phy? > > Since serdes is used for both USB and PCIe, > I can go with "phy". > >> >>> + compatible = "ti,am64-wiz-10g"; >>> + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; >>> + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; >>> + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; >>> + num-lanes = <1>; >>> + #reset-cells = <1>; >>> + #clock-cells = <1>; >>> + >>> + assigned-clocks = <&k3_clks 279 1>; >>> + assigned-clock-parents = <&k3_clks 279 5>; >>> + >>> + serdes0: serdes@f000000 { >> >> here too? > > I could use "phy" here as well. > https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/qcom/sa8775p.dtsi#L1853 > https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/renesas/r8a779f0.dtsi#L563 > >> >>> + compatible = "ti,j721e-serdes-10g"; > > [...] > >> >
On 5/8/24 6:32 PM, Roger Quadros wrote: > > > On 08/05/2024 15:34, Ravi Gunasekaran wrote: >> >> >> On 5/8/24 5:29 PM, Roger Quadros wrote: >>> >>> >>> On 29/04/2024 15:09, Ravi Gunasekaran wrote: >>>> Add SERDES0 and its wrapper description to support USB3 >>>> and SGMII interfaces. >>>> >>>> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> >>>> --- >>>> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++ >>>> 1 file changed, 54 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi >>>> index c75744edb143..beba5a3ea6cc 100644 >>>> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi >>>> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi >>>> @@ -9,6 +9,7 @@ >>>> #include <dt-bindings/interrupt-controller/irq.h> >>>> #include <dt-bindings/interrupt-controller/arm-gic.h> >>>> #include <dt-bindings/soc/ti,sci_pm_domain.h> >>>> +#include <dt-bindings/phy/phy-ti.h> >>>> >>>> #include "k3-am62p5.dtsi" >>>> >>>> @@ -75,6 +76,50 @@ >>>> <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, >>>> <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; >>>> }; >>>> + >>>> + serdes_refclk: clock-cmnrefclk { >>> >>> What could be the generic name here? >>> >> >> How about phy-clk or serdes-clk? >> I searched for "fixed-clock" and wide range of naming conventions is followed. > > We shouldn't encode the clock function in the name. How about just clk-<n> ? > where <n> is an integer starting from 0 for such fixed-clocks on the platform? > Sure. I can follow this notation. > e.g. from arch/arm64/boot/dts/ti/k3-am62p5-sk.dts > > tlv320_mclk: clk-0 { > #clock-cells = <0>; > compatible = "fixed-clock"; > clock-frequency = <12288000>; > }; > >> [...] >> >
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index c75744edb143..beba5a3ea6cc 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/ti,sci_pm_domain.h> +#include <dt-bindings/phy/phy-ti.h> #include "k3-am62p5.dtsi" @@ -75,6 +76,50 @@ <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; }; + + serdes_refclk: clock-cmnrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + serdes_wiz0: wiz@f000000 { + compatible = "ti,am64-wiz-10g"; + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <1>; + #reset-cells = <1>; + #clock-cells = <1>; + + assigned-clocks = <&k3_clks 279 1>; + assigned-clock-parents = <&k3_clks 279 5>; + + serdes0: serdes@f000000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x0f000000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 279 1>, + <&k3_clks 279 1>, + <&k3_clks 279 1>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; }; /* Main domain overrides */ @@ -83,6 +128,15 @@ ti,interrupt-ranges = <7 71 21>; }; +&main_conf { + serdes0_ln_ctrl: mux-controller@4080 { + compatible = "reg-mux"; + reg = <0x4080 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */ + }; +}; + &oc_sram { reg = <0x00 0x70000000 0x00 0x40000>; ranges = <0x00 0x00 0x70000000 0x40000>;
Add SERDES0 and its wrapper description to support USB3 and SGMII interfaces. Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com> --- arch/arm64/boot/dts/ti/k3-j722s.dtsi | 54 ++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+)